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copyright ? cirrus logic, inc. 2005 (all rights reserved) http://www.cirrus.com 110 db, 192 khz 8-ch codec with pll features ! eight 24-bit d/a, two 24-bit a/d converters ! 110 db dac / 114 db adc dynamic range ! -100 db thd+n ! system sampling rates up to 192 khz ! integrated low-jitter pll for increased system jitter tolerance ! pll clock or system clock selection ! 7 configurable general-purpose outputs ! adc high-pass filter for dc offset calibration ! expandable adc channels and one-line mode support ! digital output volume control with soft ramp ! digital +/-15 db input gain adjust for adc ! differential analog architecture ! supports logic levels between 1.8 v and 5 v general description the CS42418 codec provides two analog-to-digital and eight digital-to-analog delta-sigma converters, as well as an integrated pll. the CS42418 integrated pll provides a low-jitter sys- tem clock. the internal stereo adc is capable of independent channel gain control for single-ended or differential analog inputs. all eight channels of dac pro- vide digital volume control and differential analog outputs. the general-purpose outputs may be driven high or low, or mapped to a variety of dac mute con- trols or adc overflow indicators. the CS42418 is ideal for audio systems requiring wide dynamic range, negligible distortion and low noise, such as a/v receivers, dvd rece ivers, digital speaker and automotive audio systems. the CS42418 is available in a 64-pin lqfp package in both commercial (-10 to 70 c) and automotive (-40 to 85 c) grades. the cdb42428 customer dem- onstration board is also ava ilable for device evaluation. refer to ?ordering information? on page 71 . pll internal voltage reference rst gpo1 ad0/cs scl/cclk sda/cdout ad1/cdin vlc aouta1+ aouta1- aoutb1+ aouta3+ aouta3- aouta2- aoutb2- aouta2+ aoutb2+ aoutb1- aoutb3+ aoutb3- aouta4+ aouta4- aoutb4+ aoutb4- ainl+ ainl- ainr+ ainr- filt+ refgnd vq adc#1 adc#2 digital filter digital filter gain & clip gain & clip dac_sclk dac_lrck dac_sdin4 dac_sdin3 dac_sdin2 dac_sdin1 vls dgnd vd omck rmck lpflt int control port dac#1 dac#2 dac#3 dac#4 dac#5 dac#6 dac#7 dac#8 digital filter volume control gpo2 gpo3 gpo4 gpo5 gpo6 gpo7 mutec mute analog filter va agnd mult/div gpo level translator dac serial audio port adc_sdout adcin1 adcin2 adc_lrck adc serial audio port adc_sclk level translator november '05 ds603f1 CS42418
2 ds603f1 CS42418 table of contents 1. characteristics and specificat ions .......... ................. ................ ................ ................ ........... 6 specified operating conditions ... ................ ................. ................ ................ ................ ........... 6 absolute maximum rating s ................ ................. ................ ................ ............. ............. ........... ... 6 analog input characteristics .................................................................................................. 7 a/d digital filter characteristics .......................................................................................... 8 analog output characteristics ...................... ........................................................................ 9 d/a digital filter characteristics ........................................................................................ 10 switching characteristics ..................................................................................................... .11 switching characteristics - control port - i2c format .............................................. 12 switching characteristic s - control port - spi ? format .......................................... 13 dc electrical characteristics .............................................................................................. 14 digital interface characteristics ....................................................................................... 15 2. pin descriptions ........................................................................................................... ................. 16 3. typical connection diagrams ............................................................................................. .18 4. applications ............................................................................................................... .................... 20 4.1 overview .................................................................................................................. ....................... 20 4.2 analog inputs ............................................................................................................. ..................... 20 4.2.1 line-level inputs ....................................................................................................... ............ 20 4.2.2 high-pass filter and dc offset calibration . .......................................................................... 21 4.3 analog outputs ............................................................................................................ ................... 21 4.3.1 line-level outputs and filtering ........................................................................................ ... 21 4.3.2 interpolation filter .................................................................................................... .............. 21 4.3.3 digital volume and mute control ......................................................................................... .. 22 4.3.4 atapi specification ..................................................................................................... .......... 22 4.4 clock generation .......................................................................................................... .................. 23 4.4.1 pll and jitter attenuation .............................................................................................. ....... 23 4.4.2 omck system clock mode .................................................................................................. .24 4.4.3 master mode ............................................................................................................. ............ 24 4.4.4 slave mode .............................................................................................................. ............. 24 4.5 digital interfaces ........................................................................................................ ..................... 25 4.5.1 serial audio interface signals .......................................................................................... ..... 25 4.5.2 serial audio interface formats .............. ............................................................................ .... 27 4.5.3 adcin1/adcin2 serial data format .................................................................................... 30 4.5.4 one-line mode (olm) configurations ........ .......................................................................... 31 4.5.4.1 olm config #1 ......................................................................................................... .. 31 4.5.4.2 olm config #2 ......................................................................................................... .. 32 4.5.4.3 olm config #3 ......................................................................................................... .. 33 4.5.4.4 olm config #4 ......................................................................................................... .. 34 4.6 control port description and timing ....................................................................................... ........ 35 4.6.1 spi mode ................................................................................................................ ............... 35 4.6.2 i2c mode ................................................................................................................ ................ 36 4.7 interrupts ................................................................................................................ ........................ 37 4.8 reset and power-up ........................................................................................................ .............. 37 4.9 power supply, grounding, and pcb layout .................................................................................. 3 8 5. register quick reference ................................................................................................... ..... 39 6. register description ....................................................................................................... ........... 42 6.1 memory address pointer (map) .............................................................................................. ....... 42 6.2 chip i.d. and revision register (address 01h) (read only) .......................................................... 42 6.3 power control (address 02h) ............................................................................................... ........... 43 6.4 functional mode (address 03h) ............................................................................................. ......... 43 6.5 interface formats (address 04h) ........................................................................................... ......... 45 6.6 misc control (address 05h) ................................................................................................ ............ 46
ds603f1 3 CS42418 6.7 clock control (address 06h) ............................................................................................... ............ 48 6.8 omck/pll_clk ratio (address 07h) (read only) ....................................................................... 49 6.9 clock status (address 08h) (read only) .................................................................................... .... 50 6.10 volume transition control (address 0dh) .................................................................................. .. 51 6.11 channel mute (address 0eh) ................. .............................................................................. ......... 52 6.12 volume control ( addresses 0fh, 10h, 11 h, 12h, 13h, 14h, 15h, 16h) ...................................... 53 6.13 channel invert (address 17 h) ............................................................................................. .......... 53 6.14 mixing control pair 1 (channels a1 & b1)(address 18h) mixing control pair 2 (channels a2 & b2)(address 19h) mixing control pair 3 (channels a3 & b3)(address 1ah) mixing control pair 4 (channels a4 & b4)(address 1bh) ............................................................ 53 6.15 adc left channel gain (address 1ch) ...................................................................................... .. 55 6.16 adc right channel gain (add ress 1dh) ..................................................................................... .55 6.17 interrupt control (address 1eh) ............. ............................................................................. .......... 55 6.18 interrupt status (address 20h) (read only) ............................................................................... .. 56 6.19 interrupt mask (address 21h) .................... ......................................................................... .......... 57 6.20 interrupt mode msb (address 22h) interrupt mode lsb (address 23h) .............................................................................................. .57 6.21 mutec pin control (address 28h) .......................................................................................... ........ 57 6.22 general-purpose pin control (addresses 29h to 2fh) .... ............................................................. 58 7. parameter definitions ...................................................................................................... .......... 60 8. appendix a: external filters ............................................................................................... .... 61 8.1 adc input filter .......................................................................................................... .................... 61 8.2 dac output filter ......................................................................................................... .................. 61 9. appendix b: pll filter ..................................................................................................... ............. 62 9.1 external filter components ................................................................................................ ............ 62 9.1.1 general ................................................................................................................. ................. 62 9.1.2 capacitor selection ..................................................................................................... .......... 62 9.1.3 circuit board layout .................................................................................................... .......... 63 10. appendix c: adc filter plots ............... ................ ................ ................ ................ ............... .... 64 11. appendix d: dac filter plots ............... ................ ................ ................ ................ ............... .... 66 12. package dimensions ..................................................................................................... .......... 70 thermal characteristics ....................................................................................................... ... 70 13. ordering information ...................................................................................................... ........ 71 14. references ................................................................................................................ .................... 71 15. revision history ......................................................................................................... ................ 72 list of figures figure 1.serial audi o port master mode timing ................................................................................. ...... 11 figure 2.serial audio port slave mode timing .................................................................................. ....... 11 figure 3.control port timing - i2c format ....... .............................................................................. ............ 12 figure 4.control port timing - spi format ..................................................................................... ........... 13 figure 5.typical connection diagram .................... ....................................................................... ............ 18 figure 6.typical con nection diagram using the pll ............................................................................. ... 19 figure 7.full-scale analog input .............................................................................................. ................. 20 figure 8.full-scale output .................................................................................................... .................... 21 figure 9.atapi block diagram (x = channel pair 1, 2, 3, 4) .................................................................... .22 figure 10.clock generation .................................................................................................... .................. 23 figure 11.right-justified serial audio formats ................................................................................ ......... 27 figure 12.i2s serial audio formats ................. ........................................................................... ............... 28 figure 13.left-justified serial audio formats ................................................................................. .......... 28 figure 14.one line mode #1 serial audio format ................................................................................ .... 29 figure 15.one line mode #2 serial audio format ................................................................................ .... 29
4 ds603f1 CS42418 figure 16.adcin1/adcin2 serial audio format ................................................................................... ... 30 figure 17.olm configuration #1 ................................................................................................ ............... 31 figure 18.olm configuration #2 ................................................................................................ ............... 32 figure 19.olm configuration #3 ................................................................................................ ............... 33 figure 20.olm configuration #4 ................................................................................................ ............... 34 figure 21.control port timing in spi mode ....... .............................................................................. ......... 35 figure 22.control port timing, i2c write ......... ............................................................................. ............. 36 figure 23.control port timing, i2c read ......... .............................................................................. ............ 36 figure 24.recommended anal og input buffer ..................................................................................... ..... 61 figure 25.recommended anal og output buffer .................................................................................... ... 61 figure 26.recommended layout example .......................................................................................... ..... 63 figure 27.single-sp eed mode stopband rejection ................................................................................ .. 64 figure 28.single-sp eed mode transition band . .................................................................................. ..... 64 figure 29.single-speed mode transition band (det ail) .......................................................................... .. 64 figure 30.single-sp eed mode passband ripple ................................................................................... ... 64 figure 31.double-speed mode stopb and rejection ................................................................................ .64 figure 32.double-speed mo de transition band ................................................................................... .... 64 figure 33.double-speed mode transition band (detail) .......................................................................... 65 figure 34.double-speed mode passba nd ripple ................................................................................... .. 65 figure 35.quad-speed mode stopband rejection .................................................................................. .65 figure 36.quad-speed mode transition band ..................................................................................... .... 65 figure 37.quad-spe ed mode transition band (detail) ............................................................................ .65 figure 38.quad-speed mode passband ripple ..................................................................................... .. 65 figure 39.single-speed (fast) stopband rejection .............................................................................. ..... 66 figure 40.single-sp eed (fast) transition band ................... .............................................................. ........ 66 figure 41.single-speed (fast) transition band (detail) .......... .............................................................. ..... 66 figure 42.single-sp eed (fast) passband ripple ................. ................................................................ ...... 66 figure 43.single-sp eed (slow) stopband rejection .............................................................................. ... 66 figure 44.single-speed (slow) transition band ................................................................................. ....... 66 figure 45.single-speed (slow) transition band (detail) ........................................................................ .... 67 figure 46.single-sp eed (slow) passband ripple ...................... ........................................................... ..... 67 figure 47.double-speed (fast) stopband rejection .............................................................................. ... 67 figure 48.double-speed (fast) transition band ................................................................................. ....... 67 figure 49.double-spee d (fast) transition band (detail) ........................................................................ .... 67 figure 50.double-speed (fast) pa ssband ripple ................................................................................. ..... 67 figure 51.double-speed (slo w) stopband rejection .............................................................................. .. 68 figure 52.double-speed (slo w) transition band ................................................................................. ..... 68 figure 53.double-speed (slo w) transition band (detail) ............. ........................................................... .. 68 figure 54.double-speed (slo w) passband ripple ................................................................................. ... 68 figure 55.quad-speed (fast) stopband rejection ................................................................................ .... 68 figure 56.quad-speed (fast) transition band ................................................................................... ....... 68 figure 57.quad-speed (fast) transition band (detail) .......................................................................... .... 69 figure 58.quad-speed (fast) passb and ripple ................................................................................... ..... 69 figure 59.quad-speed (slow) stopband rejection ................................................................................ ... 69 figure 60.quad-speed (slow) transition band ...... ............................................................................. ...... 69 figure 61.quad-speed (slow) tran sition band (detail) .......................................................................... ... 69 figure 62.quad-speed (slow) passband ripple ................................................................................... .... 69
ds603f1 5 CS42418 list of tables table 1. common omck clock frequencies ............... .......................................................................... ... 24 table 2. common pll output clock fr equencies................................................................................... .. 24 table 3. slave mode clock ratios ............................................................................................... .............. 25 table 4. serial audio port channel allocations .. ............................................................................... ........ 26 table 5. dac de-emphasis ....................................................................................................... ................ 44 table 6. digital interface form ats ............................................................................................. ................. 45 table 7. adc one-line mode..................................................................................................... ............... 45 table 8. dac one-line mode..................................................................................................... ............... 45 table 9. rmck divider settings ......................... ........................................................................ ............... 48 table 10. omck frequency settings ..................... ......................................................................... .......... 48 table 11. master clock source select................ ........................................................................... ............ 49 table 12. pll clock frequency detection........................................................................................ ......... 50 table 13. example digital volume settings ........ .............................................................................. ......... 53 table 14. atapi decode ......................................................................................................... .................. 54 table 15. example adc input gain settings .......... ............................................................................ ....... 55 table 16. pll external component values ............ ............................................................................ ....... 62
6 ds603f1 CS42418 1. characteristics a nd specifications (all min/max characteristics and specifications are guaranteed over the specified operating conditions. typical performance characteristics and specifications are derive d from measurements taken at nominal supply voltages and t a = 25 c.) specified operating conditions (agnd=dgnd=0, all voltages with respect to ground; omck=12.288 mhz; master mode) absolute maximum ratings (agnd = dgnd = 0 v; all voltag es with respect to ground.) warning: operation at or beyond these limit s may result in permanent damage to the device. normal operation is not guaranteed at these extremes. notes: 1. any pin except supplies. transient currents of up to 100 ma on the analog input pins will not cause scr latch-up. 2. the maximum over/under voltage is limited by the input current. parameter symbol min typ max units dc power supply analog digital serial port interface control port interface va vd vls vlc 4.75 3.13 1.8 1.8 5.0 3.3 5.0 5.0 5.25 5.25 5.25 5.25 v v v v ambient operating temperature (power applied) CS42418-cqz CS42418-dqz t a -10 -40 - - +70 +85 c c parameters symbol min max units dc power supply analog digital serial port interface control port interface va vd vls vlc -0.3 -0.3 -0.3 -0.3 6.0 6.0 6.0 6.0 v v v v input current (note 1) i in -10ma analog input voltage (note 2) v in agnd-0.7 va+0.7 v digital input voltage serial port interface (note 2) control port interface v ind-s v ind-c -0.3 -0.3 vls+ 0.4 vlc+ 0.4 v v ambient operating temperature(power applied) CS42418-cqz CS42418-dqz t a t a -20 -50 +85 +95 c c storage temperature t stg -65 +150 c
ds603f1 7 CS42418 analog input characteristics (t a = 25 c; va = 5 v, vd = 3.3 v, logic ?0? = dgnd =agnd = 0 v; logic ?1? = vls = vlc = 5 v; measurement bandwidth is 10 hz to 20 khz unless otherwise specified. full-scale input sine wave, 997 hz.; pdn_pll = 1; omck = 12.288 mhz; single-speed mode dac_sclk = 3.072 mhz; double-speed mode dac_sclk = 6.144 mhz; quad-speed mode dac_sclk = 12.288 mhz.) notes: 3. referred to the typical full-scale voltage. 4. measured between ain+ and ain- parameter symbol CS42418-cqz min typ max CS42418-dqz min typ max unit single-speed mode (fs=48 khz) dynamic range a-weighted unweighted 108 105 114 111 - - 106 103 114 111 - - db db total harmonic distortion + noise (note 3) -1 db -20 db -60 db thd+n - - - -100 -91 -51 -94 - - - - - -100 -91 -51 -92 - - db db db double-speed mode (fs=96 khz) dynamic range a-weighted unweighted 40 khz bandwidth unweighted 108 105 - 114 111 108 - - - 106 103 - 114 111 108 - - - db db db total harmonic distortion + noise (note 3) -1 db -20 db -60 db 40 khz bandwidth -1 db thd+n - - - - -100 -91 -51 -97 -94 - - - - - - - -100 -91 -51 -97 -92 - - - db db db db quad-speed mode (fs=192 khz) dynamic range a-weighted unweighted 40 khz bandwidth unweighted 108 105 - 114 111 108 - - - 106 103 - 114 111 108 - - - db db db total harmonic distortion+ noise (note 3) -1 db -20 db -60 db 40 khz bandwidth -1 db thd+n - - - - -100 -91 -51 -97 -94 - - - - - - - -100 -91 -51 -97 -92 - - - db db db db dynamic performance for all modes interchannel isolation -110- -110-db interchannel phase deviation - 0.0001 - - 0.0001 - degree dc accuracy interchannel gain mismatch - 0.1 - - 0.1 - db gain drift - +/-100 - - +/-100 - ppm/c offset error hpf_freeze disabled hpf_freeze enabled - - 0 100 - - - - 0 100 - - lsb lsb analog input full-scale differential input voltage 1.05 va 1.10 va 1.16 va 0. 99 va 1.10 va 1.21 va vpp input impedance (differential) (note 4) 17 - - 17 - - k ? common mode rejection ratio cmrr - 82 - - 82 - db
8 ds603f1 CS42418 a/d digital filter characteristics notes: 5. the filter frequency response scales precisely with fs. 6. response shown is for fs equal to 48 kh z. filter characteristics scale with fs. parameter symbol min typ max unit single-speed mode (2 to 50 khz sample rates) passband (-0.1 db) (note 5) 0 - 0.47 fs passband ripple -- 0.035 db stopband (note 5) 0.58 - - fs stopband attenuation -95 - - db total group delay (fs = output sample rate) t gd -12/fs- s group delay variation vs. frequency ? t gd --0.0 s double-speed mode (50 to 100 khz sample rates) passband (-0.1 db) (note 5) 0 - 0.45 fs passband ripple -- 0.035 db stopband (note 5) 0.68 - - fs stopband attenuation -92 - - db total group delay (fs = output sample rate) t gd -9/fs- s group delay variation vs. frequency ? t gd --0.0 s quad-speed mode (100 to 192 khz sample rates) passband (-0.1 db) (note 5) 0 - 0.24 fs passband ripple -- 0.035 db stopband (note 5) 0.78 - - fs stopband attenuation -97 - - db total group delay (fs = output sample rate) t gd -5/fs- s group delay variation vs. frequency ? t gd --0.0 s high-pass filter characteristics frequency response -3.0 db -0.13 db (note 6) -1 20 - - hz hz phase deviation @ 20 hz (note 6) -10-deg passband ripple --0db filter setting time -10 5 /fs - s
ds603f1 9 CS42418 analog output characteristics (t a = 25 c; va = 5 v, vd = 3.3 v, logic ?0? = dgnd =agnd = 0 v; logic ?1? = vls = vlc = 5v; measurement bandwidth 10 hz to 20 khz unless otherwise specified. ; full-scale output 997 hz sine wave, test load r l = 3 k ? , c l = 30 pf; pdn_pll = 1; omck = 12.288 mhz; sing le-speed mode, dac_sclk = 3.072 mhz; double-speed mode, dac_sclk = 6.144 mhz; quad-spee d mode, dac_sclk = 12.288 mhz.) notes: 7. one-half lsb of triangular pdf dither is added to data. 8. performance limited by 16-bit quantization noise. parameter symbol CS42418-cqz min typ max CS42418-dqz min typ max unit dynamic performance for all modes dynamic range (note 7) 24-bit a-weighted unweighted 16-bit a-weighted (note 8) unweighted 104 101 - - 110 107 97 94 - - - - 102 99 - - 110 107 97 94 - - - - db db db db total harmonic distortion + noise 24-bit 0 db -20 db -60 db 16-bit 0 db (note 8) -20 db -60 db thd+n - - - - - - -100 -91 -51 -94 -74 -34 -94 - - - - - - - - - - -100 -91 -51 -94 -74 -34 -92 - - - - - db db db db db db idle channel noise/signal-to-noise ratio (a-weighted) - 110 - - 110 - db interchannel isolation (1 khz) -90 - - 90 -db analog output characteristics for all modes unloaded full-scale differential output voltage v fs .89va .94va .99va .84va .94va 1.04va vpp interchannel gain mismatch -0.1 - - 0.1 - db gain drift - 300 - - 300 - ppm/c output impedance z out - 150 - - 150 - ? ac-load resistance r l 3- -3 - -k ? load capacitance c l - - 30 - - 30 pf
10 ds603f1 CS42418 d/a digital filter characteristics notes: 9. response is clock dependent and will scale wi th fs. note that the response plots ( figures 39 to 62 ) have been normalized to fs and can be de-normalized by multiplying the x-axis scale by fs. 10. single- and double-speed mode measurement bandwidth is from stopband to 3 fs. quad-speed mode measurement bandwidth is from stopband to 1.34 fs. 11. de-emphasis is available only in single-speed mode. parameter fast roll-off slow roll-off unit min typ max min typ max combined digital and on-chip analog filter response - single-speed mode - 48 khz passband (note 9) to -0.01 db corner to -3 db corner 0 0 - - 0.4535 0.4998 0 0 - - 0.4166 0.4998 fs fs frequency response 10 hz to 20 khz -0.01 - +0.01 -0.01 - +0.01 db stopband 0.5465 - - 0.5834 - - fs stopband attenuation (note 10) 90 - - 64 - - db group delay - 12/fs - - 6.5/fs - s passband group delay deviation 0 - 20 khz - - 0.41/fs - 0.14/fs s de-emphasis error (note 11) fs = 32 khz (relative to 1 khz) fs = 44.1 khz fs = 48 khz - - - - - - 0.23 0.14 0.09 - - - - - - 0.23 0.14 0.09 db db db combined digital and on-chip analog filter response - double-speed mode - 96 khz passband (note 9) to -0.01 db corner to -3 db corner 0 0 - - 0.4166 0.4998 0 0 - - 0.2083 0.4998 fs fs frequency response 10 hz to 20 khz -0.01 - 0.01 -0.01 - 0.01 db stopband 0.5834 - - 0.7917 - - fs stopband attenuation (note 10) 80 - - 70 - - db group delay - 4.6/fs - - 3.9/fs - s passband group delay deviation 0 - 20 khz - - 0.03/fs - 0.01/fs s combined digital and on-chip analog filter response - quad-speed mode - 192 khz passband (note 9) to -0.01 db corner to -3 db corner 0 0 - - 0.1046 0.4897 0 0 - - 0.1042 0.4813 fs fs frequency response 10 hz to 20 khz -0.01 - 0.01 -0.01 - 0.01 db stopband 0.6355 - - 0.8683 - - fs stopband attenuation (note 10) 90 - - 75 - - db group delay - 4.7/fs - - 4.2/fs - s passband group delay deviation 0 - 20 khz - - 0.01/fs - 0.01/fs s
ds603f1 11 CS42418 switching characteristics (for cqz, t a = -10 to +70 c; for dqz, t a = -40 to +85 c; va = 5 v, vd =vlc= 3.3 v, vls = 1.8 v to 5.25 v; inputs: logic 0 = dgnd, logic 1 = vls, c l = 30 pf) notes: 12. after powering-up the CS42418, rst should be held low after the power supplies and clocks are set- tled. 13. see table 1 on page 24 for suggested omck frequencies 14. limit the loading on rmck to 1 cmos load if operating above 24.576 mhz. 15. not valid when rmck_div in ?clock control (address 06h)? on page 48 is set to multiply by 2. 16. 76.5 ns for single-speed and double-speed modes, 23 ns for quad-speed mode. parameters symbol min typ max units rst pin low pulse width (note 12) 1- -ms pll clock recovery sample rate range 30 - 200 khz rmck output jitter (note 14) - 200 - ps rms rmck output duty cycle (note 15) 45 50 55 % omck frequency (note 13) 1.024 - 25.600 mhz omck duty cycle (note 13) 40 50 60 % dac_sclk, adc_sclk duty cycle 45 50 55 % dac_lrck, adc_lrck duty cycle 45 50 55 % master mode rmck to dac_sclk, adc_sclk active edge delay t smd 0-15ns rmck to dac_lrck, adc_lrck delay t lmd 0-15ns slave mode dac_sclk, adc_sclk falling edge to adc_sdout, adc_sdout output valid t dpd - (note 16) ns dac_lrck, adc_lrck edge to msb valid t lrpd -26.5ns dac_sdin setup time before dac_sclk rising edge t ds 10 - - ns dac_sdin hold time after dac_sclk rising edge t dh 30 - - ns dac_sclk, adc_sclk high time t sckh 20 - - ns dac_sclk, adc_sclk low time t sckl 20 - - ns dac_sclk, adc_sclk falling to dac_lrck, sai_lrck edge t lrck -25 - +25 ns dac_sclk adc_sclk (output) rmck t smd t lmd dac_lrck adc_lrck (output) sckh sckl t t msb msb-1 t dpd adc_sdout dac_sdinx dh t ds t lrpd t lrcks t lrckd t dac_sclk adc_sclk (input) dac_lrck adc_lrck (input) figure 1. serial audio port master mode timing figure 2. serial audio port slave mode timing
12 ds603f1 CS42418 switching characteristics - control port - i2c format (for cqz, t a = -10 to +70 c; for dqz, t a = -40 to +85 c; va = 5 v, vd =v ls= 3.3 v; vlc = 1.8 v to 5.25 v; inputs: logic 0 = dgnd, logic 1 = vlc, c l =30pf) notes: 17. data must be held for sufficient ti me to bridge the transition time, t fc , of scl. 18. the acknowledge delay is based on mclk and can limit the maximum transaction speed. 19. for single-speed mode, for double-speed mode, for quad-speed mode parameter symbol min max unit scl clock frequency f scl - 100 khz rst rising edge to start t irs 500 - ns bus free time between transmissions t buf 4.7 - s start condition hold time (prior to first clock pulse) t hdst 4.0 - s clock low time t low 4.7 - s clock high time t high 4.0 - s setup time for repeated start condition t sust 4.7 - s sda hold time from scl falling (note 17) t hdd 0-s sda setup time to scl rising t sud 250 - ns rise time of scl and sda t rc -1s fall time scl and sda t fc - 300 ns setup time for stop condition t susp 4.7 - s acknowledge delay from scl falling (note 18) t ack - (note 19) ns 15 256 fs --------------------- 15 128 fs --------------------- 15 64 fs ------------------ t buf t hdst t low t hdd t high t sud stop start sda scl t irs rst t hdst t rc t fc t sust t sus p start stop repeated t rd t fd t ack figure 3. control port timing - i2c format
ds603f1 13 CS42418 switching characteristics - control port - spi ? format (for cqz, t a = -10 to +70 c; for dqz, t a = -40 to +85 c; va = 5 v, vd =vls= 3.3 v; vlc = 1.8 v to 5.25 v; inputs: logic 0 = dgnd, logic 1 = vlc, c l =30pf) notes: 20. data must be held for sufficient time to bridge the transition time of cclk. 21. for f sck <1 mhz. parameter symbol min typ max units cclk clock frequency f sck 0-6.0mhz cs high time between transmissions t csh 1.0 - - s cs falling to cclk edge t css 20 - - ns cclk low time t scl 66 - - ns cclk high time t sch 66 - - ns cdin to cclk rising setup time t dsu 40 - - ns cclk rising to data hold time (note 20) t dh 15 - - ns cclk falling to cdout stable t pd --50ns rise time of cdout t r1 --25ns fall time of cdout t f1 --25ns rise time of cclk and cdin (note 21) t r2 --100ns fall time of cclk and cdin (note 21) t f2 --100ns t r2 t f2 t dsu t dh t sch t scl cs cclk cdin t css t pd cdout t csh figure 4. control po rt timing - spi format
14 ds603f1 CS42418 dc electrical characteristics (t a = 25 c; agnd=dgnd=0, all voltages with re spect to ground; omck=12.288 mhz; master mode) notes: 22. current consumption increases with increasing fs and increasing omck. max values are based on highest fs and highest omck. variance between speed modes is negligible. 23. i lc measured with no external loading on the sda pin. 24. power-down mode is defined as rst pin = low with all clock and data lines held static. 25. valid with the recommended capacitor values on filt+ and vq as shown in figure 5 . parameter symbol min typ max units power supply current normal operation, va = 5 v (note 22) vd = 5 v vd = 3.3 v interface current, vlc=5 v (note 23) vls=5 v power-down state (all supplies) (note 24) i a i d i d i lc i ls i pd - - - - - - 75 85 51 250 13 250 - - - - - - ma ma ma a ma a power consumption (note 22) va=5 v, vd=vls=vlc=3.3 v normal operation power-down (note 24) va=5 v, vd=vls=vlc=5 v normal operation power-down (note 24) - - - - 587 1.25 866 1.25 650 - 960 - mw mw mw mw power supply rejection ratio (note 25) (1 khz) (60 hz) psrr - - 60 40 - - db db vq nominal voltage vq output impedance vq maximum allowable dc current - - - 2.7 50 0.01 - - - v k ? ma filt+ nominal voltage filt+ output impedance filt+ maximum allowable dc current - - - 5.0 35 0.01 - - - v k ? ma
ds603f1 15 CS42418 digital interface characteristics (for cqz, t a = +25 c; for dqz, t a = -40 to +85 c) notes: 26. serial port signals include: rmck, omck , adc_sclk, adc_lrck, dac_sclk, dac_lrck, a d c _ s d o u t , d a c _ s d i n 1 - 4 , a d c i n 1 / 2 control port signal s include: scl/cclk, sda/cdout, ad0/cs , ad1/cdin, int, rst 27. when operating rmck above 24.576 mhz, limit the loading on the signal to 1 cmos load. parameters (note 26) symbol min typ max units high-level input voltage serial port control port v ih 0.7xvls 0.7xvlc - - - - v v low-level input voltage serial port control port v il - - - - 0.2xvls 0.2xvlc v v high-level output voltage at i o =2 ma (note 27) serial port control port mutec, gpox v oh vls-1.0 vlc-1.0 va-1.0 - - - - - - v v v low-level output voltage at i o =2 ma (note 27) serial port, control port, mutec, gpox v ol --0.4v input leakage current i in --10 a input capacitance -8-pf mutec drive current -3-ma
16 ds603f1 CS42418 2. pin descriptions pin name # pin description dac_sdin1 dac_sdin2 dac_sdin3 dac_sdin4 1 64 63 62 dac serial audio data input ( input ) - input for two?s complement serial audio data. dac_sclk 2 dac serial clock (input/output) - serial clock for the dac serial audio interface. dac_lrck 3 dac left right clock ( input / output ) - determines which channel, left or right, is currently active on the dac serial audio data line. vd 4 51 digital power ( input ) - positive power supply for the digital section. dgnd 5 52 digital ground ( input ) - ground reference. should be connected to digital ground. vlc 6 control port power ( input ) - determines the required signal level for the control port. scl/cclk 7 serial control port clock ( input ) - serial clock for the serial control port. requires an external pull-up resistor to the logic interface voltage in i2c mode as shown in the typical connection diagram. sda/cdout 8 serial control data ( input/output ) - sda is a data i/o line in i2c mode and requires an external pull-up resistor to the logic interface vo ltage, as shown in the typical conne ction diagram. cdout is the output data line for the control port interface in spi mode. ad1/cdin 9 address bit 1 (i2c)/seri al control data (spi) ( input ) - ad1 is a chip address pin in i2c mode; cdin is the input data line for the contro l port interface in spi mode. ad0/cs 10 address bit 0 (i2c )/control port ch ip select (spi) (input ) - ad0 is a chip address pin in i2c mode; cs is the chip select signal in spi mode. int 11 interrupt (output ) - the CS42418 will generate an interrupt condition as per the interrupt mask register. see ?interrupts? on page 37 for more details. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 dac_sdin1 adc_sclk adc_lrck vd dgnd vlc scl/cclk sda/cdout ad1/cdin ad0/cs int rst ainr- ainr+ ainl+ ainl- vq filt+ refgnd aoutb4- aoutb4+ aouta4+ aouta4- va agnd aoutb3- aoutb3+ aouta3+ aouta3- aoutb2- aoutb2+ aouta2+ aouta2- aoutb1- aoutb1+ aouta1+ aouta1- mutec agnd va gpo7 gpo6 gpo5 gpo4 gpo3 gpo2 gpo1 lpflt nc nc vd dgnd vls nc rmck adc_sdout adcin2 adcin1 omck dac_lrck dac_sclk dac_sdin4 dac_sdin3 dac_sdin2 CS42418
ds603f1 17 CS42418 rst 12 reset ( input ) - the device enters a low power mode and all internal registers are reset to their default settings when low. ainr- ainr+ 13 14 differential right channel analog input ( input ) - signals are presented diffe rentially to the delta-sigma modulators via the ainr+/- pins. ainl+ ainl- 15 16 differential left channel analog input ( input ) - signals are presented differentially to the delta-sigma modulators via the ainl+/- pins. vq 17 quiescent voltage ( output ) - filter connection for internal quiescent reference voltage. filt+ 18 positive voltage reference ( output ) - positive reference voltage for the internal sampling circuits. refgnd 19 reference ground ( input ) - ground reference for the internal sampling circuits. aouta1 +,- aoutb1 +,- aouta2 +,- aoutb2 +,- aouta3 +,- aoutb3 +,- aouta4 +,- aoutb4 +,- 36,37 35,34 32,33 31,30 28,29 27,26 22,23 21,20 differential analog output ( output ) - the full-scale differential analog output level is specified in the analog characteristics specification table. va 24 41 analog power ( input ) - positive power supply for the analog section. agnd 25 40 analog ground ( input ) - ground reference. should be connected to analog ground. mutec 38 mute control ( output ) - the mute control pin outputs high impedance following an initial power-on con- dition or whenever the pdn bit is set to a ?1?, fo rcing the codec into power-down mode. the signal will remain in a high impedance state as long as the part is in power-down mode. the mute control pin goes to the selected ?active? stat e during reset, muting, or if the master clock to left/right clock frequency ratio is incorrect. this pin is intended to be used as a cont rol for external mute circuits to prevent the clicks and pops that can occur in any single supply system. the use of external mute circuits are not manda- tory but may be desired for designs requiring the absolute minimum in extraneous clicks and pops. lpflt 39 pll loop filter ( output ) - an rc network should be connected between this pin and ground. gpo7 gpo6 gpo5 gpo4 gpo3 gpo2 gpo1 42 43 44 45 46 47 48 general purpose output ( output ) - these pins can be configured as general purpose output pins, an adc overflow interrupt or mute control outputs acco rding to the general purpose pin control registers. vls 53 serial port interface power ( input ) - determines the required signal le vel for the serial port interfaces. rmck 55 recovered master clock ( output ) - recovered master clock output from the external clock reference (omck, pin 59) or the pll which is locked to the incoming adc_lrck. adc_sdout 56 adc serial data output ( output ) - output for two?s complement serial audio pcm data from the output of the internal and external adcs. adcin1 adcin2 58 57 external adc serial input ( input ) - the CS42418 provides for up to two external stereo analog to digital converter inputs to provide a maximum of six channels on one serial data output line when the CS42418 is placed in one-line mode. omck 59 external reference clock ( input ) - external clock reference that must be within the ranges specified in the register ?omck frequency (omck freqx)? on page 48 . adc_lrck 60 adc left/right clock ( input / output ) - determines which channel, left or right, is currently active on the adc serial audio data line. adc_sclk 61 adc serial clock (input/output) - serial clock for the adc serial audio interface.
18 ds603f1 CS42418 3. typical connection diagrams vls vd aouta1+ 24 0.1 f + 10 f 100 f 0.1 f + + 17 18 vq filt+ 36 37 0.1 f 4.7 f va + 10 f 0.1 f 51 53 aouta1- aoutb1+ 35 34 aoutb1- aouta2+ 32 33 aouta2- aoutb2+ 31 30 aoutb2- aouta3+ 28 29 aouta3- aoutb3+ 27 26 aoutb3- aouta4+ 22 23 aouta4- aoutb4+ 21 20 aoutb4- mutec 38 25 dgnd dgnd 5 vlc 0.1 f +1.8 v to +5 v 6 3 60 59 62 1 64 61 2 63 8 7 scl/cclk sda/cdout ad1/cdin rst 12 9 omck adc_lrck refgnd 19 ad0/cs 10 int 11 digital audio processor micro- controller 55 rmck 58 adcin1 57 adcin2 cs5361 a/d converter cs5361 a/d converter 56 adc_sdout 48 46 44 45 47 43 41 4 va vd 0.1 f agnd agnd 52 40 lpflt 39 ainl+ ainl- ainr+ ainr- 15 16 14 13 42 connect dgnd and agnd at single point near codec gpo1 gpo2 gpo3 gpo4 gpo5 gpo6 gpo7 dac_sdin1 adc_sclk dac_sdin3 dac_sdin2 dac_sdin4 dac_lrck dac_sclk 0.01 f 0.1 f + 10 f +5 v 0.01 f 0.01 f +3.3 v to +5 v + 10 f 0.1 f 0.01 f +3.3 v to +5.0 v s/pdif cs8416 receiver rmck osc optional analog output buffer 2 and mute circuit (optional) analog output buffer 2 and mute circuit (optional) analog output buffer 2 and mute circuit (optional) analog output buffer 2 and mute circuit (optional) analog output buffer 2 and mute circuit (optional) analog output buffer 2 and mute circuit (optional) analog output buffer 2 and mute circuit (optional) analog output buffer 2 and mute circuit (optional) mute drive (optional) +va * * pull up or down as required on startup if the mute control is used. * 2700 pf* 2700 pf* left analog input right analog input analog input buffer 1 analog input buffer 1 cfilt 3 rfilt 3 crip 3 2 k ? 2 k ? ** ** ** resistors are required for i 2 c control port operation 1. see the adc input filter section in the appendix. 2. see the dac output filter section in the appendix. 3. see the pll filter section in the appendix. figure 5. typical connection diagram CS42418
ds603f1 19 CS42418 vls vd aouta1+ 24 0.1 f + 10 f 100 f 0.1 f + + 17 18 vq filt+ 36 37 0.1 f 4.7 f va + 10 f 0.1 f +1.8 v to +5.0 v 51 53 aouta1- aoutb1+ 35 34 aoutb1- aouta2+ 32 33 aouta2- aoutb2+ 31 30 aoutb2- aouta3+ 28 29 aouta3- aoutb3+ 27 26 aoutb3- aouta4+ 22 23 aouta4- aoutb4+ 21 20 aoutb4- mutec 38 25 dgnd dgnd 5 vlc 0.1 f 6 3 60 59 62 1 64 61 2 63 8 7 scl/cclk sda/cdout ad1/cdin rst 12 9 omck adc_lrck refgnd 19 ad0/cs 10 int 11 dvd processor 55 rmck 58 adcin1 57 adcin2 56 adc_sdout 48 46 44 45 47 43 41 4 va vd 0.1 f agnd agnd 52 40 lpflt 39 ainl+ ainl- ainr+ ainr- 15 16 14 13 42 gpo1 gpo2 gpo3 gpo4 gpo5 gpo6 gpo7 dac_sdin1 adc_sclk dac_sdin3 dac_sdin2 dac_sdin4 dac_lrck dac_sclk 0.01 f 0.1 f + 10 f +5 v 0.01 f 0.01 f +3.3 v to +5 v + 10 f 0.1 f 0.01 f 27 mhz analog output buffer 2 and mute circuit (optional) analog output buffer 2 and mute circuit (optional) analog output buffer 2 and mute circuit (optional) analog output buffer 2 and mute circuit (optional) a nalog o utput b uffer 2 and mute circuit (optional) analog output buffer 2 and mute circuit (optional) analog output buffer 2 and mute circuit (optional) analog output buffer 2 and mute circuit (optional) mute drive (optional) * * 2700 pf* 2700 pf* left analog input right analog input analog input buffer 1 analog input buffer 1 * pull up or down as required on startup if the mute control is used. connect dgnd and agnd at single point near codec cfilt 3 rfilt 3 crip 3 2 k ? 2 k ? ** ** +va ** resistors are required for i 2 c control port operation 1. see the adc input filter section in the appendix. 2. see the dac output filter section in the appendix. 3. see the pll filter section in the appendix. figure 6. typical connection diagram using the pll CS42418
20 ds603f1 CS42418 4. applications 4.1 overview the CS42418 is a highly integrated mixed-signal 24-bit audio codec comprised of 2 analog-to-digital con- verters (adc), implemented using multi-bit delta-si gma techniques, and 8 digital-to-analog converters (dac). other functions integrated within the codec include independent digital volume controls for each dac, digital de-emphasis filters for dac, digital gain control for adc channels, adc high-pass filters, and an on-chip voltage reference. all serial data is tran smitted through one configurable serial audio interface for the adc with enhanced one-line modes of operation, allowing up to 6 channels of serial audio data on one data line. all functions are configured through a seri al control port operable in spi mode or in i2c mode. 5 and 6 show the recommended connections for the CS42418. the CS42418 operates in one of three oversampling modes based on the input sample rate. mode selection is determined by the fm bits in register ?functional mode (address 03h)? on page 43 . single-speed mode (ssm) supports input sample rates up to 50 khz and uses a 128x oversampling ratio. double-speed mode (dsm) supports input sample rates up to 100 khz and uses an oversampling ratio of 64x. quad-speed mode (qsm) supports input sample rates up to 192 khz and uses an oversampling ratio of 32x. using the integrated pll, a low-jitter clock is recove red from the adc lrck input signal. the recovered clock or an externally supplied clock attached to the omck pin can be used as the system clock. 4.2 analog inputs 4.2.1 line-level inputs ainr+, ainr-, ainl+, and ai nl- are the line-level differential analog inputs. the analog signal must be externally biased to vq, approximately 2.7 v, before being applied to these inputs. the level of the signal can be adjusted for the left and right adc independently through the adc left and right channel gain control registers on page 55 . the adc output data is in two?s co mplement binary format. for inputs above positive full scale or below negative full sca le, the adc will output 7ff fffh or 80000 0h, respec- tively and cause the adc over flow bit in the register ?interrupt status (addre ss 20h) (read only)? on page 56 to be set to a ?1?. the gpo pins may also be configured to indicate an overflow condition has occurred in the adc. see ?general-purpose pin control (addresses 29h to 2fh)? on page 58 for proper configuration. figure 7 shows the full-scale analog input levels. see ?adc input filter? on page 61 for a recommended input buffer. ain+ ain- full-scale input level= (ain+) - (ain-)= 5.6 vpp 4.1 v 2.7 v 1.3 v 4.1 v 2.7 v 1.3 v figure 7. full-scale analog input
ds603f1 21 CS42418 4.2.2 high-pass filter and dc offset calibration the high-pass filter continuously su btracts a measure of the dc offset from the output of the decimation filter. the high-pass filter can be independently enabled and disabled. if the hpf_freeze bit is set during normal operation, the current value of the dc offset for the corresponding channel is frozen and this dc offset will continue to be subtracted from the co nversion result. this feature makes it possible to perform a system dc offset calibration by: 1. running the CS42418 with the high-pass filter enabl ed until the filter settles. see the digital filter characteristics for fi lter settling time. 2. disabling the high-pass filter and freezing the stored dc offset. the high-pass filters are controlled using the hpf_freeze bit in the register ?misc control (address 05h)? on page 46 . 4.3 analog outputs 4.3.1 line-level outputs and filtering the CS42418 contains on-chip buffer amplifiers capabl e of producing line-level di fferential outputs. these amplifiers are biased to a quiescent dc level of approximately vq. the delta-sigma conversion process produces high-f requency noise beyond the audio passband, most of which is removed by the on-chip analog filters. th e remaining out-of-band noise can be attenuated using an off-chip low-pass filter. see ?dac output filter? on page 61 for a recommended output buffer. this filter configuration accounts for the normally differing ac loads on the aout+ and aout- differential output pins. it also shows an ac coupling configuration wh ich minimizes the number of required ac coupling ca- pacitors. figure 8 shows the full-scale analog output levels. 4.3.2 interpolation filter to accommodate the increasingly complex requirements of digital audio systems, the CS42418 incorpo- rates selectable interpolation filters for each mode of op eration. a ?fast? and a ?slo w? roll-off filter is avail- able in single-, double-, and quad-speed modes. these filters have been designed to accommodate a variety of musical tastes and styles. th e filt_sel bit found in the register ?misc control (address 05h)? on page 46 selects which filter is used. filt er response plots can be found in figures 39 to 62 . aout+ aout- full-scale output level= (ain+) - (ain-)= 5 vpp 3.95 v 2.7 v 1.45 v 3.95 v 2.7 v 1.45 v figure 8. full-scale output
22 ds603f1 CS42418 4.3.3 digital volume and mute control each dac?s output level is contro lled via the volume control registers operating over the range of 0 to -127 db attenuation with 0.5 db resolution. see ?volume control (addresses 0fh, 10h, 11h, 12h, 13h, 14h, 15h, 16h)? on page 53 . volume control changes are programmable to ramp in increments of 0.125 db at the rate controlled by the szc[1:0] bi ts in the digital volume control register. see ?volume transition control (address 0dh)? on page 51 . each output can be independently muted via mute control bits in the register ?channel mute (address 0eh)? on page 52 . when enabled, each xx_mute bit attenuates the corresponding dac to its maximum value (-127 db). when the xx_mute bit is disabled, the corresponding dac returns to the attenuation level set in the volume control regi ster. the attenuation is ramped up and down at the rate specified by the szc[1:0] bits. the mute control pin, mutec, is typically connected to an external mute control circuit. the mute control pin outputs high impedance during power-up or in power-down mode by setting the pdn bit in the reg- ister ?power control (address 02h)? on page 43 to a ?1?. once out of power-down mode, the pin can be controlled by the user via the control port, or automatica lly asserted high when zero data is present on all dac inputs, or when serial port clock errors are present. to prevent large transients on the output, it is desirable to mute the dac outputs before the mute control pin is asserted. please see the mutec pin in the pin descriptions section for more information. each of the gpo1-gpo7 can be programmed to provid e a hardware mute signal to individual circuits. each pin can be programmed as an output, with specific muting capabilities as de fined by the function bits in the register ?general-purpose pin control (addresses 29h to 2fh)? on page 58 . 4.3.4 atapi specification the CS42418 implements the channel-mixing func tions of the atapi cd-ro m specification. the atapi functions are applied per a-b pair. refer to table 14 on page 54 and figure 9 for additional infor- mation. ? a channel volume control aoutax aoutbx left channel audio data right channel audio data bchannel volume control mute mute dac_sdinx figure 9. atapi block diagram (x = channel pair 1, 2, 3, 4)
ds603f1 23 CS42418 4.4 clock generation the clock generation for the CS42418 is shown in the figure below. the internal mclk is derived from the output of the pll or a master clock source attached to omck. the mux selection is controlled by the sw_ctrlx bits and can be configured to manual switch mode only, or automatically switch on loss of pll lock to the other so urce input. 4.4.1 pll and jitter attenuation the pll can be configured to lock onto the incoming adc_lrck signal from the adc serial port and generate the required internal master clock frequency. there are some applications where low jitter in the recovered clock, presented on the rmck pin, is important. for this reason, the pll has been designed to have good jitter-attenuation char acteristics. by setting the pll_lr ck bit to a ?1? in the register ?clock control (address 06h)? on page 48 , the pll will lock to the incoming adc_lrck and ge nerate an output master clock (rmck) of 256fs. table 2 shows the output of the pll with typical input fs values for adc_lrck. see ?appendix b: pll filter? on page 62 for more information concerning pll operation, required filter components, optimal layout guidelines, and jitter-attenuation characteristics. adc_lrck (slave mode) pll (256fs) 8.192 - 49.152 mhz 00 01 pll_lrck bit sw_ctrlx bits (manual or auto switch) omck auto detect input clock 1,1.5, 2, 4 single speed 256 double speed 128 quad speed 64 single speed 4 double speed 2 quad speed 1 00 01 10 00 01 10 00 01 10 00 01 10 not olm olm #1 dac_fmx bits adc_fmx bits dac_olx or adc_olx bits adc_olx and adc_sp selx bits adc_sclk dac_sclk dac_lrck adc_lrck rmck olm #2 not olm olm #1 olm #2 128fs 256fs 128fs 256fs internal mclk 00 01 10 11 rmck_divx bits 2 4 x2 figure 10. clock generation
24 ds603f1 CS42418 4.4.2 omck syst em clock mode a special clock-switching mode is ava ilable that allows the clock that is input through the omck pin to be used as the internal master clock. this feature is controlled by the sw_ctrlx bits in register ?clock con- trol (address 06h)? on page 48 . an advanced auto-switching mode is also implemented to maintain mas- ter clock functionality. the clock auto-switching mode allows the clock input through omck to be used as a clock in the system without any disruption when th e pll loses lock, for example, when the lrck is re- moved from adc_lrck. this clock-switching is done glitch-free. a clock adhering to the specifications detailed in the switching characteristics table on page 11 must be applied to the omck pin at all times that the frc_pll_lk bit is set to ?0? (see ?force pll lock (frc_pll_lk)? on page 49 ). 4.4.3 master mode in master mode, the serial interfac e timings are derived from an external clock attached to omck or from the output of the pll with an input reference to the adc_lrck input from the adc serial port. the dac serial port and adc serial port can both be masters only when omck is used as the clock source. when using the pll output, the adc serial port must be slave and the dac serial port can operate in master mode. master clock selection and operation is configur ed with the sw_ctrl1:0 bits in the clock control register (see ?clock control (address 06h)? on page 48 ). 4.4.4 slave mode in slave mode, dac_lrck, dac_sclk and/or adc_ lrck and adc_sclk operate as inputs. the left/right clock signal must be equal to the sample rate, fs, and must be synchronously derived from the supplied master clock, omck, or must be synchronous to the supplied adc_lrck used as the input to the pll. in this latter scenario, the pll output becom es the internal master cl ock. the supported pll out- put frequencies are shown in table 2 . the serial bit clock, dac_sclk and/or adc_sc lk, must be synchronous to the corresponding dac_lrck/adc_lrck and be equal to 128x, 64x, 48x or 32x fs, depending on the interface format se- lected and desired speed mode. sample rate (khz) omck (mhz) single-speed (4 to 50 khz) double-speed (50 to 100 khz) quad-speed (100 to 192 khz) 256x 384x 512x 128x 192x 256x 64x 96x 128x 48 12.2880 18.4320 24.5760 - - - - - - 96 - - - 12.2880 18.4320 24.5760 - - - 192 - - - - - - 12.2880 18.4320 24.5760 table 1. common omck clock frequencies sample rate (khz) pll output (mhz) single-speed (4 to 50khz) double-speed (50 to 100khz) quad-speed (100 to 192khz) 256x 256x 256x 32 8.1920 - - 44.1 11.2896 - - 48 12.2880 - - 64 - 16.3840 - 88.2 - 22.5792 - 96 - 24.5760 - 176.4 - - 45.1584 192 - - 49.1520
ds603f1 25 CS42418 when the device is clocked from omck, the frequency of omck must be at le ast twice the frequency of the fastest slave mode, sclk. for exam ple, if both serial ports are in slave mode with one sclk running at 32x fs and the other at 64x fs, the slowest omck signal that can be used to clock the device is 128x fs. when either serial port is in sl ave mode, its respective lrck signal must be present for proper device operation. in slave mode, one-line mode #1 is supported; one-line mode #2 is not. the sample rate to omck ratios and omck frequen cy requirements for slave mode operation are shown in table 1 . refer to table 3 for required clock ratios. 4.5 digital interfaces 4.5.1 serial audio interface signals the CS42418 interfaces to an external digital a udio processor via two independent serial ports, the dac serial port, dac_sp, and the adc serial port, ad c_sp. the digital output of the internal adcs use the adc_sdout pin and can be configured to use eith er the adc or dac serial port timings.these con- figuration bits and the selection of single-, double- or quad-speed mode for dac_sp and adc_sp are found in register ?functional mode (address 03h)? on page 43 . the serial interface clocks, adc_ sclk for adc_sp and dac_sclk for dac_sp, are used for transmit- ting and receiving audio data. either adc_sclk or dac_sclk can be generated by the CS42418 (mas- ter mode), or it can be input from an external sour ce (slave mode). master or slave mode selection is made using bits dac_sp m/s and adc_sp m/s in register ?misc control (address 05h)? on page 46 . the left/right clock (adc_lrck or dac_lrck) is us ed to indicate left and right data frames and the start of a new sample period. it may be an output of th e CS42418 (master mode), or it may be generated by an external source (slave mode). as described in later sections, particular modes of operation do allow the sample rate, fs, of the adc_sp and the dac_sp to be different, but must be multiples of each other. the serial data interface format selection (left/ri ght-justified, i2s or one-line mode) for the adc serial port data out pin, adc_sdout, and the dac input pins, dac_sdin1:4, is co nfigured using the appro- priate bits in the register ?interface formats (address 04h)? on page 45 . the serial audio data is presented in two's complement binary form with the msb first in all formats. dac_sdin1, dac_sdin2, dac_sdin 3and dac_sdin4 are the serial data input pins supplying the in- ternal dac. adc_sdout, the adc data output pin, carries data from the two internal 24-bit adcs and, when configured for one-line mode, up to four addition al adc channels attached externally to the signals adcin1 and adcin2 (typically two cs5361 stereo a dcs). when operated in one-line mode, 6 channels of dac data are input on dac_sdin1, two additi onal dac channels on dac_sdin4, and 6 channels of adc data are output on adc_sdout. table 4 on page 26 outlines the serial port channel allocations. single-speed double-speed quad-speed one-line mode #1 omck/lrck ratio 256x, 384x, 512x 128x, 192x, 256x 64x, 96x, 128x 256x sclk/lrck ratio 32x, 48x, 64x, 128x 32x, 48x, 64x 32x, 48x, 64x 128x table 3. slave mode clock ratios
26 ds603f1 CS42418 serial inputs / outputs dac_sdin1 left channel right channel one-line mode dac #1 dac #2 dac channels 1,2,3,4,5,6 dac_sdin2 left channel right channel one-line mode dac #3 dac #4 not used dac_sdin3 left channel right channel one-line mode dac #5 dac #6 not used dac_sdin4 left channel right channel one line mode dac #7 dac #8 dac channels 7,8 adc_sdout left channel right channel one-line mode adc #1 adc #2 adc channels 1,2,3,4,5,6 adcin1 left channel right channel external adc #3 external adc #4 adcin2 left channel right channel external adc #5 external adc #6 table 4. serial audio port channel allocations
ds603f1 27 CS42418 4.5.2 serial audio interface formats the dac_sp and adc_sp digital audio serial ports support five formats with varying bit depths from 16 to 24 as shown in figures 11 to 15 . these formats are selected using the configuration bits in the registers, ?functional mode (address 03h)? on page 43 and ?interface formats (address 04h)? on page 45 . for the diagrams below, single-speed mode is equivalent to fs = 32, 44.1, 48 khz; double-speed mode is for fs = 64, 88.2, 96 khz; and quad-spe ed mode is for fs = 176.4, 196 khz. left channel right channel 6543210 987 15 14 13 12 11 10 6543210 987 15 14 13 12 11 10 dac_sdinx adc_sdout dac_lrck adc_lrck dac_sclk adc_sclk figure 11. right-justified serial audio formats right-justified mode, data valid on rising edge of sclk bits/sample sclk rate(s) notes master slave 16 64 fs 48, 64, 128 fs single-speed mode 64 fs 64 fs double-speed mode 64 fs 64 fs quad-speed mode 24 64, 128, 256 fs 64, 128 fs single-speed mode 64 fs 64 fs double-speed mode 64 fs 64 fs quad-speed mode
28 ds603f1 CS42418 left channel right channel dac_sdinx adc_sdout +3 +2 +1 +5 +4 -1 -2 -3 -4 -5 +3 +2 +1 +5 +4 -1 -2 -3 -4 msb msb lsb lsb dac_lrck adc_lrck dac_sclk adc_sclk figure 12. i2s serial audio formats i2s mode, data valid on rising edge of sclk bits/sample sclk rate(s) notes master slave 16 64 fs 48, 64, 128 fs single-speed mode 64 fs 64 fs double-speed mode 64 fs 64 fs quad-speed mode 18 to 24 64, 128, 256 fs 48, 64, 128 fs single-speed mode 64 fs 64 fs double-speed mode 64 fs 64 fs quad-speed mode dac_lrck adc_lrck dac_sclk adc_sclk left channel right channel dac_sdinx adc_sdout +3 +2 +1 +5 +4 -1 -2 -3 -4 -5 +3 +2 +1 +5 +4 -1 -2 -3 -4 msb lsb msb lsb figure 13. left-justifi ed serial audio formats left-justified mode, data valid on rising edge of sclk bits/sample sclk rate(s) notes master slave 16 64 fs 32, 48, 64, 128 fs single-speed mode 64 fs 32, 64 fs double-speed mode 64 fs 32, 64 fs quad-speed mode 18 to 24 64, 128, 256 fs 48, 64, 128 fs single-speed mode 64 fs 64 fs double-speed mode 64 fs 64 fs quad-speed mode
ds603f1 29 CS42418 dac_lrck adc_lrck dac_sclk adc_sclk lsb msb 20 clks 64 clks 64 clks lsb msb lsb msb lsb msb lsb msb lsb msb msb dac1 dac3 dac5 dac2 dac4 dac6 20 clks 20 clks 20 clks 20 clks 20 clks left channel right channel 20 clks dac7 dac8 20 clks dac_sdin4 20 clks adc1 adc3 adc5 adc2 adc4 adc6 20 clks 20 clks 20 clks 20 clks 20 clks adc_sdout dac_sdin1 figure 14. one line mode #1 serial audio format one line data mode #1, data valid on rising edge of sclk bits/sample sclk rate(s) notes master slave 20 128 fs 128 fs single-speed mode 128 fs 128fs double-speed mode lsb msb 24 clks 128 clks lsb msb lsb msb lsb msb lsb msb lsb msb msb dac1 dac3 dac5 dac2 dac4 dac6 24 clks 24 clks 24 clks 24 clks 24 clks left channel right channel 24 clks dac7 dac8 24 clks 24 clks adc1 adc3 adc5 adc2 adc4 adc6 24 clks 24 clks 24 clks 24 clks 24 clks 128 clks dac_lrck adc_lrck dac_sclk adc_sclk adc_sdout dac_sdin1 dac_sdin4 figure 15. one line mode #2 serial audio format one line data mode #2, data valid on rising edge of sclk bits/sample sclk rate(s) notes master slave 24 256 fs not supported single-speed mode
30 ds603f1 CS42418 4.5.3 adcin1/adcin2 se rial data format the two serial data lines which interface to the op tional external adcs, adcin1 and adcin2, support only left-justified, 24-bit sa mples at 64fs or 128fs. this interface is not affected by any of the serial port configuration register bit settings. these serial da ta lines are used when supporting one-line mode of operation with external adcs attached. if these signa ls are not being used, they should be tied together and wired to gnd via a pull-down resistor. for proper operation, the CS42418 must be configured to select which sclk/lrck is being used to clock the external adcs. the ext adc sclk bit in register ?misc control (address 05h)? on page 46 must be set accordingly. set this bit to ?1? if the external adcs are wired using the dac_sp clocks. if the adcs are wired to use the adc_sp clocks, set this bit to ?0?. dac_lrck adc_lrck dac_sclk adc_sclk left channel right channel adcin1/2 +3 +2 +1 +5 +4 -1 -2 -3 -4 -5 +3 +2 +1 +5 +4 -1 -2 -3 -4 msb lsb msb lsb figure 16. adcin1/adcin2 serial audio format left-justified mode, data valid on rising edge of sclk bits/sample sclk rate(s) notes 24 64, 128 fs single-speed mode, fs= 32, 44.1, 48 khz 64 fs double-speed mode, fs= 64, 88.2, 96 khz not supported quad-speed mo de, fs= 176.4, 192 khz
ds603f1 31 CS42418 4.5.4 one-line mode (olm) configurations 4.5.4.1 olm config #1 one-line mode configuration #1 can support up to 8 channels of dac data, and 6 channels of adc data. this is the only configuration whic h will support up to 24-bit samples at a sampling frequency of 48 khz on all channels for both the dac and adc. register / bit settings description functional mode register (addr = 03h) set dac_fmx = adc_fmx = 00,01,10 dac_lrck must equal adc_lrck; sample rate conversion not supported set adc_clk_sel = 0 configure adc_sdout to be cloc ked from the dac_sp clocks. interface format register (addr = 04h) set difx bits to proper serial format select the digital interface format when not in one-line mode set adc_olx bits = 00,01,10 select adc operating mode, see table below for valid combinations set dac_olx bits = 00,01,10 select dac operating mode, see table below for valid combinations misc. control register (addr = 05h) set dac_sp m/s = 1 configure dac serial port to master mode. set adc_sp m/s = 1 configure adc serial port to master mode. set ext adc sclk = 0 identify external adc clock source as sai serial port. dac mode not one-line mode one- line mode #1 one-line mode #2 adc mode not one- line mode dac_sclk=64fs dac_lrck=ssm/dsm/qsm dac_sclk=128fs dac_lrck=ssm/dsm adc_sclk=64fs adc_lrck=dac_lrck not valid one-line mode #1 dac_sclk=128fs dac_lrck=ssm/dsm adc_sclk=64fs adc_lrck=dac_lrck dac_sclk=128fs dac_lrck=ssm/dsm adc_sclk=64fs adc_lrck=dac_lrck not valid one-line mode #2 dac_sclk=256fs dac_lrck=ssm adc_sclk=64fs adc_lrck=dac_lrck not valid dac_sclk=256fs dac_lrck=ssm adc_sclk=64fs adc_lrck=dac_lrck sclk_port1 lrck_port1 sdin_port1 sclk_port2 lrck_port2 sdout1_port2 sdout2_port2 sdout3_port2 sdout4_port2 adc_sclk adc_lrck dac_sclk dac_lrck adc_sdout dac_sdin1 dac_sdin2 dac_sdin3 dac_sdin4 rmck adcin1 adcin2 mclk sdout1 sdout2 lrck sclk 64fs adc data 64fs,128fs, 256fs digital audio processor cs5361 cs5361 mclk figure 17. olm configuration #1 CS42418
32 ds603f1 CS42418 4.5.4.2 olm config #2 this configuration will support up to 8 channels of dac data or 6 chan nels of adc data and will handle up to 20-bit samples at a sampling-frequency of 96 khz on all channels for both the dac and adc. the output data stream of the internal and external adcs is configured to use the adc_ sdout output and run at the dac serial port sample frequency. register / bit settings description functional mode register (addr = 03h) set dac_fmx = 00,01,10 dac_lrck can run at ssm, dsm or qsm independent of adc_lrck set adc_fmx = 00,01,10 adc_lrck can run at ssm, dsm or qsm independent of dac_lrck set adc_clk_sel = 1 configure adc_sdout to be clocked from the adc_sp clocks. interface format register (addr = 04h) set difx bits to proper serial format select the digital interface format when not in one-line mode set adc_olx bits = 00,01,10 select adc operating mode, see table below for valid combinations set dac_olx bits = 00,01 select dac operating mode, see table below for valid combinations misc. control register (addr = 05h) set dac_sp m/s = 1 set dac serial port to master mode. set adc_sp m/s = 1 set adc serial port to master mode. set ext adc sclk = 1 identify external adc clock s ource as dac serial port. dac mode not one-line mode one- line mode #1 one-line mode #2 adc mode not one- line mode dac_sclk=64fs dac_lrck=ssm/dsm/qsm adc_sclk=64fs adc_lrck=ssm/dsm/qsm dac_sclk=128fs dac_lrck=ssm adc_sclk=64fs adc_lrck=ssm/dsm/qsm not valid one-line mode #1 dac_sclk=64fs dac_lrck=ssm/dsm adc_sclk=128fs adc_lrck=dac_lrck dac_sclk=128fs dac_lrck=ssm adc_sclk=128fs adc_lrck=dac_lrck not valid one-line mode #2 dac_sclk=64fs dac_lrck=ssm adc_sclk=256fs adc_lrck=dac_lrck not valid not valid sclk_port1 lrck_port1 sdin_port1 sclk_port2 lrck_port2 sdout1_port2 sdout2_port2 sdout3_port2 sdout4_port2 rmck adcin1 adcin2 mclk sdout1 sdout2 lrck sclk 64fs,128fs adc data 64fs,128fs, 256fs digital audio processor cs5361 cs5361 adc_sclk adc_lrck adc_sdout dac_sclk dac_lrck dac_sdin1 dac_sdin2 dac_sdin3 dac_sdin4 mclk figure 18. olm configuration #2 CS42418
ds603f1 33 CS42418 4.5.4.3 olm config #3 this configuration will support up to 8 channels of dac data and 6 ch annels of adc data. olm config #3 will handle up to 20-bit adc samples at an fs of 48 khz and 24-bit dac samples at an fs of 48 khz. since the adc?s data stream is configured to use the ad c_sdout output and the internal and external adcs are clocked from the adc_sp, the sample rate for th e dac serial port can be different from the sample rate of the adc serial port. register / bit settings description functional mode register (addr = 03h) set dac_fmx = 00,01,10 dac_lrck can run at ssm, dsm, or qsm independent of adc_lrck set adc_fmx = 00,01,10 adc_lrck can run at ssm, dsm, or qsm independent of dac_lrck set adc_clk_sel = 1 configure adc_sdout to be clocked from the adc_sp clocks. interface format register (addr = 04h) set difx bits to proper serial format select the digital interface format when not in one-line mode set adc_olx bits = 00,01 select adc operating mode, see table below for valid combinations set dac_olx bits = 00,01,10 select dac operating mode, see table below for valid combinations misc. control register (addr = 05h) set dac_sp m/s = 1 set dac serial port to master mode. set adc_sp m/s = 0 or 1 set adc serial port to master mode or slave mode. set ext adc sclk = 0 identify external adc clock s ource as adc serial port. dac mode not one-line mode one- line mode #1 one-line mode #2 adc mode not one- line mode dac_sclk=64fs dac_lrck=ssm/dsm/qsm adc_sclk=64fs adc_lrck=ssm/dsm/qsm dac_sclk=128fs dac_lrck=ssm/dsm adc_sclk=64fs adc_lrck=ssm/dsm/qsm dac_sclk=256fs dac_lrck=ssm adc_sclk=64fs adc_lrck=ssm/dsm/qsm one-line mode #1 dac_sclk=64fs dac_lrck=ssm/dsm/qsm adc_sclk=128fs adc_lrck=ssm dac_sclk=128fs dac_lrck=ssm/dsm adc_sclk=128fs adc_lrck=ssm dac_sclk=256fs dac_lrck=ssm adc_sclk=128fs adc_lrck=ssm one-line mode #2 not valid not valid not valid sclk_port1 lrck_port1 sdin_port1 sclk_port2 lrck_port2 sdout1_port2 sdout2_port2 sdout3_port2 sdout4_port2 rmck adcin1 adcin2 mclk sdout1 sdout2 lrck sclk 64fs,128fs digital audio processor cs5361 cs5361 adc_sclk adc_lrck adc_sdout dac_sclk dac_lrck dac_sdin1 dac_sdin2 dac_sdin3 dac_sdin4 mclk 64fs,128fs,256fs figure 19. olm configuration #3 CS42418
34 ds603f1 CS42418 4.5.4.4 olm config #4 this one-line mode configuration can support up to 8 channels of dac data on 2 dac_sdin pins and 2 channels of adc data and will handle up to 24-bit samples at a sampling frequency of 48 khz on all chan- nels for both the dac and adc. the output data stream of the internal adcs can be configured to run at the dac_sp clock speeds or to run at the adc_sp rate. the dac_sp and adc_sp can operate at differ- ent fs rates. register / bit settings description functional mode register (addr = 03h) set dac_fmx = 00,01,10 dac_lrck can run at ssm, dsm, or qsm independent of adc_lrck set adc_fmx = 00,01,10 adc_lrck can run at ssm, dsm, or qsm independent of dac_lrck set adc_clk_sel = 0 or 1 configure adc_sdout to be clocked from the adc_sp or dac_sp clocks. interface format register (addr = 04h) set difx bits to proper serial format select the digital interface format when not in one-line mode set adc_olx bits = 00 set adc operating mode to not one- line mode since only 2 channels of adc are supported set dac_olx bits = 00,01,10 select dac oper ating mode, see table below for valid combinations misc. control register (addr = 05h) set dac_sp m/s = 0 or 1 set dac serial port to master mode or slave mode. set adc_sp m/s = 0 or 1 set adc serial port to master mode or slave mode. set ext adc sclk = 0 external adcs are not used. leave bit in default state. dac mode not one-line mode one- line mode #1 one-line mode #2 adc mode not one- line mode dac_sclk=64fs/128fs dac_lrck=ssm/dsm/qsm adc_sclk=64fs/128fs adc_lrck=ssm/dsm/qsm dac_sclk=128fs dac_lrck=ssm/dsm adc_sclk=64fs/128fs adc_lrck=ssm/dsm/qsm dac_sclk=256fs dac_lrck=ssm adc_sclk=64fs/128fs adc_lrck=ssm/dsm/qsm one-line mode #1 not valid not valid not valid one-line mode #2 not valid not valid not valid sclk_port1 lrck_port1 sdin_port1 sdin_port2 sclk_port2 lrck_port2 sdout1_port2 sdout2_port2 sdout3_port2 sdout4_port2 rmck adcin1 adcin2 64fs,128fs, 256fs digital audio processor adc_sclk adc_lrck adc_sdout dac_sclk dac_lrck dac_sdin1 dac_sdin2 dac_sdin3 dac_sdin4 64fs,128fs mclk figure 20. olm configuration #4 CS42418
ds603f1 35 CS42418 4.6 control port description and timing the control port is used to access the registers, allowing the CS42418 to be configured for the desired op- erational modes and formats. the operation of the cont rol port may be complete ly asynchronous with re- spect to the audio sample rates. however, to avoid potential interference problems, the control port pins should remain static if no operation is required. the control port has two modes: spi and i2c, with the CS42418 acting as a slave device. spi mode is se- lected if there is a high-to-low transition on the ad0/cs pin after the rst pin has been brought high. i2c mode is selected by connecting the ad0/cs pin through a resistor to vlc or dgnd, thereby permanently selecting the desired ad0 bit address state. 4.6.1 spi mode in spi mode, cs is the CS42418 chip-select signal; cclk is the control port bit clock (input into the CS42418 from the microcontroller); cdin is the i nput data line from the microcontroller, and cdout is the output data line to the microcontroller. data is cl ocked in on the rising edge of cclk and out on the falling edge. figure 21 shows the operation of the control port in spi mode. to write to a register, bring cs low. the first seven bits on cdin form the chip address and mu st be 1001111. the eighth bit is a read/write indi- cator (r/w ), which should be low to write. the next eight bits form the memory address pointer (map), which is set to the address of the r egister that is to be updated. the ne xt eight bits are the data which will be placed into the register designated by the map. during writes, the cdout output stays in the hi-z state. it may be externally pulled high or low with a 47 k ? resistor, if desired. there is a map auto-increment capab ility, enabled by the incr bit in th e map register. if incr is a zero, the map will stay constant for successive read or writ es. if incr is set to a 1, the map will auto-increment after each byte is read or wr itten, allowing block reads or wr ites of successive registers. to read a register, the map has to be set to the correct address by executing a partial write cycle which finishes (cs high) immediately after the map byte. the m ap auto increment bit (incr) may be set or not, as desired. to begin a read, bring cs low, send out the chip address and set the read/write bit (r/w ) high. the next falling edge of cclk will clock out the msb of the addressed register (cdout will leave the high impedance state). if the map auto-i ncrement bit is set to 1, the da ta for successive registers will appear consecutively. map msb lsb data byte 1 byte n r/w r/w address chip address chip cdin cclk cs cdout msb lsb msb lsb 1001111 1001111 map = memory address pointer, 8 bits, msb first high impedance figure 21. control port timing in spi mode
36 ds603f1 CS42418 4.6.2 i2c mode in i2c mode, sda is a bidirectional da ta line. data is clocke d into and out of the pa rt by the clock, scl. there is no cs pin. pins ad0 and ad1 form the two least-si gnificant bits of the chip address and should be connected through a resistor to vlc or dgnd as de sired. the state of the pins is sensed while the CS42418 is being reset. the signal timings for a read and write cycle are shown in figure 22 and figure 23 . a start condition is defined as a falling transition of sda while the clock is high. a stop condition is a rising transition while the clock is high. all other transitions of sda occur while the clock is low. the first byte sent to the CS42418 after a start condition consists of a 7-bit chip address field and a r/w bit (high for a read, low for a write). the upper 5 bits of the 7-bit address field are fixed at 10011. to communicate with a CS42418, the chip address field, which is the first byte sent to the CS42418, should match 10011, followed by the settings of the ad1 and ad0. the eighth bit of the address is the r/w bit. if the operation is a write, the next byte is the memory address poin ter (map) which selects the register to be read or written. if the op- eration is a read, the cont ents of the register poin ted to by the map will be out put. setting the auto-incre- ment bit in map allows successive reads or writes of consecutive registers. each byte is separated by an acknowledge bit. the ack bit is output from the CS42418 after each input byte is read and is input to the CS42418 from the microcontroller after each transmitted byte. since the read operation cannot set the map, an aborte d write operation is used as a preamble. as shown in figure 23 , the write operation is aborted after the acknowledge for the map byte by sending a stop con- dition. the following pseudocode illu strates an aborted wr ite operation followed by a read operation. send start condition. send 10011xx0 (chip address & write operation). receive acknowledge bit. send map byte, auto increment off. receive acknowledge bit. send stop condition, aborting write. 4 5 6 7 24 25 scl chip address (write) map byte data data +1 start ack stop ack ack ack 1 0 0 1 1 ad1 ad0 0 sda incr 6 5 4 3 2 1 0 7 6 1 0 7 6 1 0 7 6 1 0 0 1 2 3 8 9 12 16 17 18 19 10 11 13 14 15 27 28 26 data +n figure 22. control port timing, i2c write scl chip address (write) map byte data data +1 start ack stop ack ack ack 1 0 0 1 1 ad1 ad0 0 sda 1 0 0 1 1 ad1 ad0 1 chip address (read) start incr 6 5 4 3 2 1 0 7 0 7 0 7 0 no 16 8 9 12 13 14 15 4 5 6 7 0 1 20 21 22 23 24 26 27 28 2 3 10 11 17 18 19 25 ack data + n stop figure 23. control port timing, i2c read
ds603f1 37 CS42418 send start condition. send 10011xx1(chip address & read operation). receive acknowledge bit. receive byte, contents of selected register. send acknowledge bit. send stop condition. setting the auto increment bit in th e map allows successive reads or wr ites of consecutiv e registers. each byte is separated by an acknowledge bit. 4.7 interrupts the CS42418 has a comprehensive inte rrupt capability. the in t output pin is intended to drive the interrupt input pin on the host microcontroller. the int pin may be set to be active low, active high or active low with no active pull-up transistor. this last mode is used for active low, wired-or hook -ups, with multiple periph- erals connected to the microcontroller interrupt input pin. many conditions can cause an interrupt, as listed in the interrupt status register descriptions (see ?interrupt status (address 20h) (read only)? on page 56 ). each source may be masked off through mask register bits. in addition, each source may be set to rising edge, fall ing edge, or level-sensitive. combined with the option of level-sensitive or edge-sensitive modes within the microcontroller, many different configurations are pos- sible, depending on the needs of the equipment designer. 4.8 reset and power-up reliable power-up can be accomplished by keeping the de vice in reset until the power supplies, clocks and configuration pins are stable. it is also recommended th at reset be activated if the analog or digital supplies drop below the recommended operating conditi on to prevent power-glitch-related issues. when rst is low, the CS42418 enters a low-power mode and all internal states are reset, including the control port and registers, and the outputs are muted. when rst is high, the control port becomes opera- tional, and the desired settings should be loaded into the control registers. writi ng a 0 to the pdn bit in the power control register will th en cause the part to leave the low-powe r state and begin ope ration. if the in- ternal pll is selected as the clock source, the serial audio outputs will be enable d after the pll has settled (see ?power control (address 02h)? on page 43 for more details). the delta-sigma modulators settle in a matter of micros econds after the analog se ction is powered, either through the application of power or by setting the rst pin high. however, the voltage reference will take much longer to reach a final value due to the presen ce of external capacitance on the filt+ pin. a time delay of approximately 80 ms is required after applying power to the device or after exiting a reset state. during this voltage reference ramp delay, all serial ports and dac outp uts will be automatically muted.
38 ds603f1 CS42418 4.9 power supply, gr ounding, and pcb layout as with any high-resolution converter, the CS42418 requires careful attention to power supply and ground- ing arrangements if its potential pe rformance is to be realized. figure 5 and 6 show the recommended power arrangements, with va connected to clean supplies. vd, which powers the digital circuitry, may be run from the system logic supply. alternatively, vd may be powered from the analog supply via a ferrite bead. in this case, no additional devices should be powered from vd. for applications where the output of the pll is requir ed to be low jitter, use a separate, low-noise analog +5 v supply for va, decoupled to agnd. in addition, a separate region of analog ground plane around the filt+, vq, lpflt, re fgnd, agnd, and va pins is recommended. extensive use of power and ground planes, ground plane fill in un used areas and surf ace mount decoupling capacitors are recommended. decoupling capacitors shoul d be as near to the pins of the CS42418 as pos- sible. the low value ceramic capacitor should be the nearest to the pin and should be mounted on the same side of the board as the CS42418 to minimize inductance effects. all signals, especially clocks, should be kept away from the filt+, vq and lpflt pins in order to avoid unwanted coupling into the modulators and pll. the filt+ and vq decoupling capacitors, particular ly the 0.1 f, must be positioned to minimize the electrical path from filt+ and refgnd. the cdb424 28 evaluation board demonstrates the optimum lay- out and power supply arrangements.
ds603f1 39 CS42418 5. register qu ick reference addr function 7 6 5 4 3 2 1 0 01h id chip_id3 chip_id2 chip_id1 chip_i d0 rev_id3 rev_id2 rev_id1 rev_id0 page 42 default 1110xxxx 02h power con- trol reserved pdn_pll pdn_adc pdn_dac4 pdn_dac3 pdn_dac2 pdn_dac1 pdn page 43 default 0 0 00000 1 03h functional mode dac_fm1 dac_fm0 adc_fm1 adc_fm0 reserved adc_clk sel dac_dem reserved page 43 default 0 0 00000 0 04h interface formats dif1 dif0 adc_ol1 adc_ol0 dac_ol1 dac_ol0 reserved codec_rj16 page 45 default 0 1 00000 0 05h misc control ext adc sclk hiz_rmck reserved freeze filtsel hpf_ freeze dac_sp m/s adc_sp m/s page 46 default 0 0 00000 0 06h clock con- trol rmck_div1 rmck_div0 omck freq1 omck freq0 pll_lrck sw_ctrl1 sw_ctrl0 frc_pll_lk page 48 default 0 0 00000 0 07h omck/pll_ clk ratio ratio7 ratio6 ratio5 ratio4 ratio3 ratio2 ratio1 ratio0 page 49 default xxxxxxx x 08h clock status reserved reserved reserved reserved active_clk pll_clk2 pll_clk1 pll_clk0 page 50 default xxxxxxx x 09h- 0ch reserved reserved reserved reserved reserved reserved reserved reserved reserved default x x x x x x x x 0dh volume control reserved sngvol szc1 szc0 amute reserved ramp_up ramp_dn page 51 default 0 0 00100 0 0eh channel mute b4_mute a4_mute b3_mute a3_mute b2_mute a2_mute b1_mute a1_mute page 52 default 0 0 00000 0 0fh vol. control a1 a1_vol7 a1_vol6 a1_vol5 a1_vol4 a1_vol3 a1_vol2 a1_vol1 a1_vol0 page 53 default 0 0 00000 0 10h vol. control b1 b1_vol7 b1_vol6 b1_vol5 b1_vol4 b1_vol3 b1_vol2 b1_vol1 b1_vol0 page 53 default 0 0 00000 0 11h vol. control a2 a2_vol7 a2_vol6 a2_vol5 a2_vol4 a2_vol3 a2_vol2 a2_vol1 a2_vol0 page 53 default 0 0 00000 0 12h vol. control b2 b2_vol7 b2_vol6 b2_vol5 b2_vol4 b2_vol3 b2_vol2 b2_vol1 b2_vol0 page 53 default 0 0 00000 0
40 ds603f1 CS42418 13h vol. control a3 a3_vol7 a3_vol6 a3_vol5 a3_vol4 a3_vol3 a3_vol2 a3_vol1 a3_vol0 page 53 default 0 0 00000 0 14h vol. control b3 b3_vol7 b3_vol6 b3_vol5 b3_vol4 b3_vol3 b3_vol2 b3_vol1 b3_vol0 page 53 default 0 0 00000 0 15h vol. control a4 a4_vol7 a4_vol6 a4_vol5 a4_vol4 a4_vol3 a4_vol2 a4_vol1 a4_vol0 page 53 default 0 0 00000 0 16h vol. control b4 b4_vol7 b4_vol6 b4_vol5 b4_vol4 b4_vol3 b4_vol2 b4_vol1 b4_vol0 page 53 default 0 0 00000 0 17h channel invert inv_b4 inv_a4 inv_b3 inv_a3 inv_b2 inv_a2 inv_b1 inv_a1 page 53 default 0 0 00000 0 18h mixing ctrl pair 1 p1_a=b reserved reserved p1_atapi4 p1_atapi3 p1_atapi2 p1_atapi1 p1_atapi0 page 53 default 0 0 00100 1 19h mixing ctrl pair 2 p2_a=b reserved reserved p2_atapi4 p2_atapi3 p2_atapi2 p2_atapi1 p2_atapi0 page 53 default 0 0 00100 1 1ah mixing ctrl pair 3 p3_a=b reserved reserved p3_atapi4 p3_atapi3 p3_atapi2 p3_atapi1 p3_atapi0 page 53 default 0 0 00100 1 1bh mixing ctrl pair 4 p4_a=b reserved reserved p4_atapi4 p4_atapi3 p4_atapi2 p4_atapi1 p4_atapi0 page 53 default 0 0 00100 1 1ch adc left ch. gain reserved reserved lgain5 lgain4 lgain3 lgain2 lgain1 lgain0 page 55 default 0 0 00000 0 1dh adc right ch. gain reserved reserved rgain5 rgain4 rgain3 rgain2 rgain1 rgain0 page 55 default 0 0 00000 0 1eh interrupt control sp_sync reserved de-emph1 de-emph0 int1 int0 reserved reserved page 55 default 0 0 00000 0 1fh reserved reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 00000 0 20h interrupt status unlock reserved reserved reserved reserved reserved overflow reserved page 56 default xxxxxxx x 21h interrupt mask unlockm reserved reserved reserved reserved reserved overflowm reserved page 57 default 0 0 00000 0 22h interrupt mode msb unlock1 reserved reserved reserved reserved reserved of1 reserved page 57 default 0 0 00000 0 addr function 7 6 5 4 3 2 1 0
ds603f1 41 CS42418 23h interrupt mode lsb unlock0 reserved reserved reserved reserved reserved of0 reserved page 57 default 0 0 00000 0 24h- 27h reserved reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 00000 0 28h mutec reserved reserved mcpolarity m_aouta1 m_aoutb1 m_aouta2 m_aoutb2 m_aouta3 m_aoutb3 m_aouta4 m_aoutb4 page 57 default 0 0 01111 1 29h gpo7 mode1 mode0 polarity function4 function3 function2 function1 function0 page 58 default 0 0 00000 0 2ah gpo6 mode1 mode0 polarity function4 function3 function2 function1 function0 page 58 default 0 0 00000 0 2bh gpo5 mode1 mode0 polarity function4 function3 function2 function1 function0 page 58 default 0 0 00000 0 2ch gpo4 mode1 mode0 polarity function4 function3 function2 function1 function0 page 58 default 0 0 00000 0 2dh gpo3 mode1 mode0 polarity function4 function3 function2 function1 function0 page 58 default 0 0 00000 0 2eh gpo2 mode1 mode0 polarity function4 function3 function2 function1 function0 page 58 default 0 0 00000 0 2fh gpo1 mode1 mode0 polarity function4 function3 function2 function1 function0 page 58 default 0 0 00000 0 addr function 7 6 5 4 3 2 1 0
42 ds603f1 CS42418 6. register description all registers are read/write except for the i.d. and revision register, omck/pll_clk ratio register, clock status and interrupt status register which are read only. see the following bit definition tables for bit assignment informa- tion. the default state of each bit after a power-up sequence or reset is listed in each bit description. 6.1 memory address pointer (map) not a register 6.1.1 increment (incr) default = 1 function: memory address pointer auto increment control 0 - map is not incremented automatically. 1 - internal map is automatically incremented after each read or write. 6.1.2 memory address pointer (mapx) default = 0000001 function: memory address pointer (m ap). sets the register address that will be read or writte n by the control port. 6.2 chip i.d. and revision register (address 01h) (read only) 6.2.1 chip i.d. (chip_idx) default = 1110 function: i.d. code for the CS42418. permanently set to 1110. 6.2.2 chip revision (rev_idx) default = xxxx function: CS42418 revision level. revision c1 is coded as 0101 revision c is coded as 0011. 76543210 incr map6 map5 map4 map3 map2 map1 map0 76543210 chip_id3 chip_id2 chip_id1 chip_id0 rev_id3 rev_id2 rev_id1 rev_id0
ds603f1 43 CS42418 6.3 power control (address 02h) 6.3.1 power down pll (pdn_pll) default = 0 function: when enabled, the pll is held in a reset state. it is advised that any change of this bit be made while the dacs are muted or the power- down bit (pdn) is enabled to elim inate the possib ility of audible artifacts. 6.3.2 power down adc (pdn_adc) default = 0 function: when enabled the stereo analog to digital converter will remain in a re set state. it is advised that any change of this bit be made while the dacs are mute d or the power-down bit (pdn) is enabled to elim- inate the possibility of audible artifacts. 6.3.3 power down dac pairs (pdn_dacx) default = 0 function: when enabled the respective dac channel pair x (aoutax and aoutbx ) will remain in a reset state. 6.3.4 power down (pdn) default = 1 function: the entire device will enter a low-po wer state when this function is enabled, and the c ontents of the control registers are retained in this mode. the power-down bit defaults to ?enabled? on power-up and must be disabled before normal operation can occur. 6.4 functional mode (address 03h) 6.4.1 dac functional mode (dac_fmx) default = 00 00 - single-speed mode (4 to 50 khz sample rates) 01 - double-speed mode (50 to 100 khz sample rates) 10 - quad-speed mode (100 to 192 khz sample rates) 11 - reserved function: selects the required range of sample rates for all converters clocked from the dac serial port (dac_sp). bits must be set to the corresponding sample rate range when the dac_sp is in master or slave mode. 76543210 reserved pdn_pll pdn_adc pdn_dac4 pdn_dac3 pdn_dac2 pdn_dac1 pdn 76543210 dac_fm1 dac_fm0 adc_fm1 adc_fm0 rese rved adc_sp sel dac_dem reserved
44 ds603f1 CS42418 6.4.2 adc functional mode (adc_fmx) default = 00 00 - single-speed mode (4 to 50 khz sample rates) 01 - double-speed mode (50 to 100 khz sample rates) 10 - quad-speed mode (100 to 192 khz sample rates) 11 - reserved function: selects the required range of sample rates for the adc serial port (adc_sp). these bits must be set to the corresponding sample rate range when the adc_sp is in master or slave mode. 6.4.3 adc clock source select (adc_clk sel) default = 0 0 - adc_sdout clocked from the dac_sp. 1 - adc_sdout clocked from the adc_sp. function: selects the desired clocks for the adc serial output. 6.4.4 dac de-emphasis control (dac_dem) default = 0 function: enables the digital filter to maintain the standard 15 s/50 s digital de-emphasis filter response at the auto-detected sample rate of either 32, 44.1, or 48 khz. de-e mphasis will not be e nabled, regardless of this register setting, at any ot her sample rate. if the frc_pll_lk bi t is set to a ?1?b, the auto-detect sample rate feature is disabled. to apply the corr ect de-emphasis filter, use the de-emph bits in the interrupt control (address 1eh) register to set the appropriate sample rate. dac_dem reg03h[1] frc_pll_lk reg06h[0] de-emph[1:0] reg1eh[5:4] de-emphasis mode 0 x xx no de-emphasis 1 0 xx auto-detect fs 11 00 01 10 11 reserved 32 khz 44.1 khz 48 khz table 5. dac de-emphasis
ds603f1 45 CS42418 6.5 interface formats (address 04h) 6.5.1 digital interface format (difx) default = 01 function: these bits select the digital interface format used for the adc & dac serial port when not in one-line mode. the required relationship between the left/right clock, serial clock, and serial data is defined by the digital interface format and the options are detailed in figures 11 - 13 . 6.5.2 adc one_line mode (adc_olx) default = 00 function: these bits select which mode the adc will use. by default, one-line mode is disabled, but it can be selected using these bits. please see figures 14 and 15 to see the format of one-line mode 1 and one-line mode 2. 6.5.3 dac one_line mode (dac_olx) default = 00 function: these bits select which mode the dac will use. by default, one-line mode is disabled, but it can be selected using these bits. please see figures 14 and 15 to see the format of one-line mode 1 and one-line mode 2. 76543210 dif1 dif0 adc_ol1 adc_ol0 dac_ol1 dac_ol0 reserved codec_rj16 dif1 dif0 description format figure 00 left-justified, up to 24-bit data 0 13 01 i2s, up to 24-bit data 1 12 10 right-justified, 16-bit or 24-bit data 2 11 11 reserved -- table 6. digital interface formats adc_ol1 adc_ol0 description format figure 00 dif: take the dif setting from reg04h[7:6] -- 01 one-line #1 3 14 10 one-line #2 4 15 11 reserved -- table 7. adc one-line mode dac_ol1 dac_ol0 description format figure 00 dif: take the dif setting from reg04h[7:6] -- 01 one-line #1 3 14 10 one-line #2 4 15 11 reserved -- table 8. dac one-line mode
46 ds603f1 CS42418 6.5.4 codec right-justified bits (codec_rj16) default = 0 function: this bit determines how many bits to use during rig ht-justified mode for the dac and adc. by de- fault, the dac and adc will be in rj24 bits, but can be set to rj16 bits. 0 - 24 bit mode. 1 - 16 bit mode. 6.6 misc control (address 05h) 6.6.1 external adc sclk select (ext adc sclk) default = 0 function: this bit identifies the sclk source for the exter nal adcs attached to the adcin1/2 ports when using one-line mode of operation. 0 - adc_sclk is used as external adc sclk. 1 - dac_sclk is used as external adc sclk. 6.6.2 rmck high impedance (hiz_rmck) default = 0 function: this bit is used to create a high-impedance outpu t on rmck when the clock signal is not required. 6.6.3 freeze controls (freeze) default = 0 function: this function will freeze the previo us output of, and allow modificati ons to be made to, the volume control (address 0fh-16h), channel invert (address 17h), and mixing control pair (address 18h-1bh) registers without the changes taking effect until the freeze is disabled. to make multiple changes in these control port registers take effect simult aneously, enable the freeze bit, make all register changes, then disable the freeze bit. 76543210 ext adc sclk hiz_rmck reserved f reeze filt_sel hpf_freeze dac_sp m/s adc_sp m/s
ds603f1 47 CS42418 6.6.4 interpolation fi lter select (filt_sel) default = 0 function: this feature allows the user to se lect whether the dac interpolation f ilter has a fast- or slow roll-off. for filter characteri stics, please see ?d/a digital filter char acteristics? on page 10 . 0 - fast roll-off. 1 - slow roll-off. 6.6.5 high-pass filter freeze (hpf_freeze) default = 0 function: when this bit is set, the internal high-pass filter for the selected channel will be disabled. the current dc offset value will be frozen and continue to be subtracted from the conversion result. see ?a/d dig- ital filter characteristics? on page 8 . 6.6.6 dac serial port mast er/slave select (dac_sp m/s ) default = 0 function: in master mode, dac_sclk and dac_lrck are outpu ts. internal dividers will divide the master clock to generate the serial clock and left/right clock. in slave mode, dac_sclk and dac_lrck become inputs. if the dac_sp is in slave mode, dac_lrck must be present for proper device operation. 6.6.7 adc serial port mast er/slave select (adc_sp m/s ) default = 0 function: in master mode, adc_sclk and adc_lrck are outpu ts. internal dividers will divide the master clock to generate the serial clock and left/right clock. in slave mode, adc_sclk and adc_lrck become inputs. if the adc_sp is in slave mode, adc_lrck must be present for proper device operation. to use the pll to lock to adc_lrck, the adc_sp must be in slave mode. when using the pll to lock to lrck, if adc_sdout is configured to be clocked by the adc_sp, both adc_sclk and adc_lrck must be present. if adc_sdout is config ured to be clocked by the dac_sp, only the adc_lrck signal must be applied.
48 ds603f1 CS42418 6.7 clock control (address 06h) 6.7.1 rmck divide (rmck_divx) default = 00 function: divides/multiplies the internal mclk, either from the pll or omck, by the selected factor. 6.7.2 omck frequency (omck freqx) default = 00 function: sets the appropriate frequency for the supplied omck. 6.7.3 pll lock to lrck (pll_lrck) default = 0 0 - disabled 1 - enabled function: when enabled, the in ternal pll of the CS42418 will lock to the adc_lrck of the adc serial port (adc_lrck) while the adc_sp is in slave mode. 76543210 rmck_div1 rmck_div0 omck freq1 omck freq0 pll_lrck sw_ctrl1 sw_ctrl0 frc_pll_lk rmck_div1 rmck_div0 description 00 divide by 1 01 divide by 2 10 divide by 4 11 multiply by 2 table 9. rmck divider settings omck freq1 omck freq0 description 0 0 11.2896 mhz or 12.2880 mhz 0 1 16.9344 mhz or 18.4320 mhz 1 0 22.5792 mhz or 24.5760 mhz 11reserved table 10. omck frequency settings
ds603f1 49 CS42418 6.7.4 master clock source select (sw_ctrlx) default = 00 function: these two bits, along with the unlock bit in register ?interrupt status (address 20h) (read only)? on page 56 , determine the master clock source for the CS42418. when sw_ctrl1 and sw_ctrl0 are set to '00'b, selecting the output of the pll as the internal clock source, and the pll becomes unlocked, rmck will equal omck, but all internal and serial port timings are not valid. when the frc_pll_lk bit is set to ?1?b, the sw_ctrlx bits must be set to ?00?b. if the pll becomes unlocked when the f rc_pll_lk bit is set to ?1?b, rmck will not equal omck. 6.7.5 force pll lock (frc_pll_lk) default = 0 function: this bit is used to enable the pll to lock to t he adc_lrck with the absence of a clock signal on omck. when set to a ?1?b, the auto-detect sample fr equency feature will be disabled and the sw_ctrlx bits must be set to ?00?b. the omck/p ll_clk ratio (address 07h) (read only) register contents are not valid, and the pll_clk[2:0] bits will be set to ?111?b. use th e de-emph[1:0] bits to properly apply de-emphasis filtering. 6.8 omck/pll_clk ratio (address 07h) (read only) 6.8.1 omck/pll_clk ratio (ratiox) default = xxxxxxxx function: this register allows the user to find the exact ab solute frequency of the recovered mclk coming from the pll. this value is represented as an integer (ratio7:6) and a fractional (ratio5:0) part. for example, an omck/pll_clk ratio of 1.5 would be displayed as 60h. sw_ctrl1 sw_ctrl0 unlock description 0 0 x manual setting, mclk sourced from pll. 0 1 x manual setting, mclk sourced from omck. 10 0 1 hold, keep same mclk source.auto switch, mclk sourced from omck. 11 0 1 auto switch, mclk sourced from pll. auto switch, mclk sourced from omck. table 11. master clock source select 76543210 ratio7(2 1 )ratio6(2 0 )ratio5(2 -1 )ratio4(2 -2 ) ratio3(2 -3 )ratio2(2 -4 ) ratio1(2 -5 )ratio0(2 -6 )
50 ds603f1 CS42418 6.9 clock status (address 08h) (read only) 6.9.1 system clock selection (active_clk) default = x 0 - output of pll 1 - omck function: this bit identifies the source of the internal system clock (mclk). 6.9.2 pll clock frequency (pll_clkx) default = xxx function: the CS42418 detects the ratio between the omck an d the recovered clock from the pll. given the absolute frequency of omck, this ratio may be used to determine the absolute frequency of the pll clock. if a 12.2880 mhz, 18.4320 mhz, or 24.5760 mhz clock is applied to omck and the omck_freqx bits are set accordingly (see ?omck frequency (omck freqx)? on page 48 ), the absolute frequency of the pll clock is reflected in the pll_clkx bits according to table 14 . if the absolute frequency of the pll clock does not match one of the frequencies given in table 14 , these bits will reflect the clos- est available value. if the frequency of omck is not equal to 12.2 880 mhz, 18.4320 mhz, or 24.5760 mhz, the contents of the pll_clkx bits will be inaccura te and should be disreg arded. in this case, an external controller may use the contents of the omck/pll_clk ratio register and the known omck frequency to de- termine the absolute frequency of the pll clock. note: these bits are set to ?111?b when the frc_pll_lk bit is ?1?b. 76543210 reserved reserved reserved reserved active_clk pll_clk2 pll_clk1 pll_clk0 pll_clk2 pll_clk1 pll_clk0 description 0 0 0 8.1920 mhz 0 0 1 11.2896 mhz 0 1 0 12.288 mhz 0 1 1 16.3840 mhz 1 0 0 22.5792 mhz 1 0 1 24.5760 mhz 1 1 0 45.1584 mhz 1 1 1 49.1520 mhz table 12. pll clock frequency detection
ds603f1 51 CS42418 6.10 volume transition control (address 0dh) 6.10.1 single volume control (sngvol) default = 0 function: the individual channel volume levels are independen tly controlled by their respective volume control registers when this function is disabled. when enabled, the volume on all channels is determined by the a1 channel volume control register and the other volume control registers are ignored. 6.10.2 soft ramp and zero cross control (szcx) default = 00 00 - immediate change 01 - zero cross 10 - soft ramp 11 - soft ramp on zero crossings function: immediate change when immediate change is selected, all level c hanges will take effect i mmediately in one step. zero cross zero cross enable dictates that signal-level changes, either by attenuation change s or muting, will occur on a signal zero crossing to minimize audi ble artifacts. th e requested leve l-change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 khz sample rate) if the signal does not encou nter a zero crossing. the zero cross function is independently mon- itored and implemented for each channel. soft ramp soft ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramping, in 1/8 db steps, from the current level to the new level at a rate of 1 db per 8 left/right clock periods. soft ramp on zero crossing soft ramp and zero cross enable dictates that sig nal level changes, either by attenuation changes or muting, will occur in 1/8 db step s and be implemented on a signal zero crossing. the 1/8 db level change will occur after a timeout pe riod between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 khz sample rate) if the signal does not enc ounter a zero crossing. the zero cross function is independently monitored and implemented for each channel. 76543210 reserved sngvol szc1 szc0 amute mute adc_sp ramp_up ramp_dn
52 ds603f1 CS42418 6.10.3 auto-mute (amute) default = 1 0 - disabled 1 - enabled function: the digital-to-analog converters of the CS42418 wi ll mute the output following the reception of 8192 consecutive audio samples of static 0 or -1. a single sa mple of non-static da ta will release the mute. detection and muting is done independently for ea ch channel. the quiescent voltage on the output will be retained, and t he mutec pin will go active during the mute period. the muting function is af- fected, similar to volume cont rol changes, by the soft and zero cross bits (szc[1:0]). 6.10.4 soft volume ramp-up after error (rmp_up) default = 0 0 - disabled 1 - enabled function: an un-mute will be performed after executing a filter mode change , after a mclk/lrck ratio change or error, and after changing the functional mode. when this feature is enabled, this un-mute is affect- ed, similar to attenuation changes, by the soft and zero cross bits (szc[1 :0]). when disabled, an immediate un-mute is perf ormed in these instances. note: for best results, it is recommended that this bit be used in conjunction with the rmp_dn bit. 6.10.5 soft ramp-down before filter mode change (rmp_dn) default = 0 0 - disabled 1 - enabled function: a mute will be performed prior to executing a filter mode or de-emphasis mode change. when this feature is enabled, this mute is affected, similar to attenuation changes, by the soft and zero cross bits (szc[1:0]). when disabled, an immediate mute is performed prior to executing a filter mode or de-emphasis mode change. note: for best results, it is recommended that this bit be used in conjunction with the rmp_up bit. 6.11 channel mute (address 0eh) 6.11.1 independent chan nel mute (xx_mute) default = 0 0 - disabled 1 - enabled function: the digital-to-analog converter ou tputs of the CS42418 will mute when enabled. the quiescent volt- age on the outputs will be re tained. the muting function is affe cted, similar to attenuation changes, by the soft and zero cross bits (szc[1:0]). 76543210 b4_mute a4_mute b3_mute a3_mute b2_mute a2_mute b1_mute a1_mute
ds603f1 53 CS42418 6.12 volume control (addresses 0fh, 10h, 11h, 12h, 13h, 14h, 15h, 16h) 6.12.1 volume control (xx_vol) default = 0 function: the digital volume control register s allow independent control of the signal levels in 0.5 db incre- ments from 0 to -127 db. volume settings are decoded as shown in table 13 . the volume changes are implemented as dictated by the soft and zero cross bits (szc[1:0]). all volume settings less than -127 db are equivalent to enabling the mute bit for the given channel. 6.13 channel invert (address 17h) 6.13.1 invert signal polarity (inv_xx) default = 0 0 - disabled 1 - enabled function: when enabled, these bits will invert the sign al polarity of their respective channels. 6.14 mixing control pair 1 (channels a1 & b1)(address 18h) mixing control pair 2 (channels a2 & b2)(address 19h) mixing control pair 3 (channels a3 & b3)(address 1ah) mixing control pair 4 (channels a4 & b4)(address 1bh) 6.14.1 channel a volume = channel b volume (px_a=b) default = 0 0 - disabled 1 - enabled function: the aoutax and aoutbx volume levels are indep endently controlled by the a and the b channel volume control registers when this function is disabled. the volume on both aoutax and aoutbx are determined by the a channel vo lume control registers (per a-b pair), and the b channel volume control registers are ignored when this function is enabled. 76543210 xx_vol7 xx_vol6 xx_vol5 xx_vol4 xx _vol3 xx_vol2 xx_vol1 xx_vol0 binary code decimal value volume setting 00000000 0 0 db 00101000 40 -20 db 01010000 80 -40 db 01111000 120 -60 db 10110100 180 -90 db table 13. example digital volume settings 76543210 inv_b4 inv_a4 inv_b3 inv_a3 inv_b2 inv_a2 inv_b1 inv_a1 76543210 px_a=b reserved reserved px_atapi4 px_atapi3 px_atapi2 px_atapi1 px_atapi0
54 ds603f1 CS42418 6.14.2 atapi channel-mixing and muting (px_atapix) default = 01001 function: the CS42418 implements the channel-mixing func tions of the atapi cd-rom specification. the atapi functions are applied per a-b pair. refer to table 14 and figure 9 for additional information. atapi4 atapi3 atapi2 atapi1 atapi0 aoutax aoutbx 00000 mute mute 00001 mute br 00010 mute bl 00011 mute b[(l+r)/2] 00100 ar mute 00101 ar br 00110 ar bl 00111 ar b[(l+r)/2] 01000 al mute 01001 al br 01010 al bl 01011 al b[(l+r)/2] 01100 a[(l+r)/2] mute 0 1 1 0 1 a[(l+r)/2] br 0 1 1 1 0 a[(l+r)/2] bl 0 1 1 1 1 a[(l+r)/2] b[(l+r)/2] 10000 mute mute 10001 mute br 10010 mute bl 10011 mute [(al+br)/2] 10100 ar mute 10101 ar br 10110 ar bl 10111 ar [(bl+ar)/2] 11000 al mute 11001 al br 11010 al bl 11011 al [(al+br)/2] 1 1 1 0 0 [(al+br)/2] mute 1 1 1 0 1 [(al+br)/2] br 1 1 1 1 0 [(bl+ar)/2] bl 1 1 1 1 1 [(al+br)/2] [(al+br)/2] table 14. atapi decode
ds603f1 55 CS42418 6.15 adc left channel gain (address 1ch) 6.15.1 adc left channel gain (lgainx) default = 00h function: the level of the left analog channel can be adjusted in 1 db increments as dictated by the soft and zero cross bits (szc[1:0]) from +15 to -15 db. levels are decoded in two?s complement, as shown in table 15 . 6.16 adc right channel gain (address 1dh) 6.16.1 adc right channel gain (rgainx) default = 00h function: the level of the right analog channel can be adjusted in 1 db increments as dictated by the soft and zero cross bits (szc[1:0]) from +15 to -15 db. levels are decoded in two?s complement, as shown in table 15 . 6.17 interrupt control (address 1eh) 6.17.1 serial port sync hronization (sp_sync) default = 0 0 - dac & adc serial port timings not in phase 1 - dac & adc serial port timings are in phase function: forces the lrck and sclk from the dac & adc serial ports to align and operate in phase. this function will operate when both po rts are running at the same sample rate or when operating at dif- ferent sample rates. 76543210 reserved reserved lgain5 lgai n4 lgain3 lgain2 lgain1 lgain0 76543210 reserved reserved rgain5 rgai n4 rgain3 rgain2 rgain1 rgain0 binary code decimal value volume setting 001111 +15 +15 db 001010 +10 +10 db 000101 +5 +5 db 000000 0 0 db 111011 -5 -5 db 110110 -10 -10 db 110001 -15 -15 db table 15. example adc input gain settings 76543210 sp_sync reserved de-emph1 de-emph0 int1 int0 reserved reserved
56 ds603f1 CS42418 6.17.2 de-emphasis select bits (de-emphx) default = 00 00 - reserved 01 - de-emphasis for 32 khz sample rate. 10 - de-emphasis for 44.1 khz sample rate. 11 - de-emphasis for 48 khz sample rate. function: used to specify which de-emphasis filter to apply when the ?force pll lock (frc_pll_lk)? on page 49 is enabled. 6.17.3 interrupt pin control (intx) default = 00 00 - active high; high output indicates interrupt condition has occurred 01 - active low; low output indicates an interrupt condition has occurred 10 - open drain, active low. requires an external pull-up resistor on the int pin. 11 - reserved function: determines how the interrupt pin (int) will indicate an interrupt condition. 6.18 interrupt status (address 20h) (read only) for all bits in this register, a ?1? means the associated interrupt condition has occurred at least once since the reg- ister was last read. a ?0? means the associated interrupt condition has not occurred since the last reading of the register. reading the register resets a ll bits to 0. status bits that are masked off in t he associated mask register will always be ?0? in this register. 6.18.1 pll unlock (unlock) default = 0 function: pll unlock status bit. this bit will go high if the pll becomes unlocked. 6.18.2 adc overflow (overflow) default = 0 function: indicates that there is an over-range condition anywhere in the CS42418 adc signal path. 76543210 unlock reserved reserved reserved reserved reserved overflow reserved
ds603f1 57 CS42418 6.19 interrupt mask (address 21h) default = 00000000 function: the bits of this register serve as a mask fo r the interrupt sources found in the register ?interrupt status (address 20h) (read only)? on page 56 . if a mask bit is set to 1, th e error is unmasked, meaning that its occurrence will affect the int pin and the status register . if a mask bit is se t to 0, the error is masked, meaning that its o ccurrence will not affe ct the int pin or the status register. the bit positions align with the corresponding bits in the interrupt status register. 6.20 interrupt mode msb (address 22h) interrupt mode lsb (address 23h) default = 00000000 function: the two interrupt mode registers form a 2-bit code for each interrupt status register function. there are three ways to set the int pin active in accordance with the interrupt condition. in the rising edge active mode, the int pin becomes ac tive on the arrival of the interr upt condition. in the falling edge active mode, the int pin becomes active on the re moval of the interrupt condition. in level active mode, the int interrupt pin becomes active during the interrupt condition. be aware that the active level (active high or low) only depends on th e int(1:0) bits located in the register ?interrupt control (address 1eh)? on page 55 . 00 - rising edge active 01 - falling edge active 10 - level active 11 - reserved 6.21 mutec pin control (address 28h) 6.21.1 mutec polarity select (mcpolarity) default = 0 0 - active low 1 - active high function: determines the polarity of the mutec pin. 76543210 unlockm reserved reserved reserved reserved reserved overflowm reserved 76543210 unlock1 reserved reserved reserved reserved reserved of1 reserved unlock0 reserved reserved reserved reserved reserved of0 reserved 76543210 reserved reserved mcpolarity m_aouta1 m_aoutb1 m_aouta2 m_aoutb2 m_aouta3 m_aoutb3 m_aouta4 m_aoutb4
58 ds603f1 CS42418 6.21.2 channel mutes select (m_aoutxx) default = 11111 0 - channel mute is not mapped to the mutec pin 1 - channel mute is mapped to the mutec pin function: determines which channel mutes will be mapped to the mutec pin. if no channel mute bits are mapped, then the mutec pin is driven to the ?activ e? state as defined by the polarity bit. these channel mute select bits are ?anded? together in order for the mutec pin to go active. this means that if multiple channel mutes are selected to be mapped to the mutec pin, all corresponding chan- nels must be mute d before the mutec will go active. 6.22 general-purpose pin control (addresses 29h to 2fh) 6.22.1 mode control (modex) default = 00 00 - reserved 01 - mute mode 10 - gpo/overflow mode 11 - gpo, drive high mode function: mute mode - the pin is configured as a dedicated mute pin. the muting function is controlled by the function bits. gpo, drive low / adc overflow mode - the pin is configured as a general-purpose output driven low or as a dedicated adc overflow pin indicating an over-range condition anywhere in the adc signal path for either the left or right channel. the functi onx bits determine the operation of the pin. when configured as a gpo with the output driven low, the driver is a cmos driver. when configured to iden- tify an adc overflow condition, the driver is an open drain driver requiring a pull-up resistor. gpo, drive high mode - the pin is configured as a general purpose output driven high. 6.22.2 polarity select (polarity) default = 0 function: mute mode - if the pin is configured as a dedicated mute output pin, the polarity bit determines the polarity of the mapped pin according to the following 0 - active low 1 - active high gpo, drive low / adc overflow mode - if the pin is configured as a gpo, drive low / adc overflow mode pin, the polarity bit is ignored. it is reco mmended that in this mode this bit be set to 0. gpo, drive high - if the pin is configured as a general-purpo se output driven high, the polarity bit is ignored. it is recommended that in this mode this bit be set to 0. 76543210 mode1 mode0 polarity function4 function3 function2 function1 function0
ds603f1 59 CS42418 6.22.3 functional co ntrol (functionx) default = 00000 function: mute mode - if the pin is configured as a dedicated mute pin, the functional bits determine which chan- nel mutes will be mapped to this pi n according to the following table. 0 - channel mute is not mapped to the gpox pin 1 - channel mute is mapped to the gpox pin: gpo, drive low / adc overflow mode - if the pin is configured as a gpo, drive low / adc overflow mode pin, the function1 and function0 bits determine how th e output will behave according to the following table. it is recommended that in this mode the remaining functional bits be set to 0. gpo, drive high - if the pin is configured as a general-pu rpose output, the functional bits are ignored and the pin is driven high. it is recommended that in this mode all the functional bits be set to 0. gpox reg address function4 function3 function2 function1 function0 gpo7 pin 42 29h m_aouta1 m_aoutb1 m_aouta2 m_aoutb2 m_aouta3 m_aoutb3 m_aouta4 m_aoutb4 gpo6 pin 43 2ah m_aouta1 m_aoutb1 m_aouta2 m_aoutb2 m_aouta3 m_aoutb3 m_aouta4 m_aoutb4 gpo5 pin 44 2bh m_aouta1 m_aoutb1 m_aouta2 m_aoutb2 m_aouta3 m_aoutb3 m_aouta4 m_aoutb4 gpo4 pin 45 2ch m_aouta1 m_aoutb1 m_aouta2 m_aoutb2 m_aouta3 m_aoutb3 m_aouta4 m_aoutb4 gpo3 pin 46 2dh m_aouta1 m_aoutb1 m_aouta2 m_aoutb2 m_aouta3 m_aoutb3 m_aouta4 m_aoutb4 gpo2 pin 47 2eh m_aouta1 m_aoutb1 m_aouta2 m_aoutb2 m_aouta3 m_aoutb3 m_aouta4 m_aoutb4 gpo1 pin 48 2fh m_aouta1 m_aoutb1 m_aouta2 m_aoutb2 m_aouta3 m_aoutb3 m_aouta4 m_aoutb4 function1 function0 gpox driver type 0 0 drive low cmos 1 1 ovfl r or l open drain
60 ds603f1 CS42418 7. parameter definitions dynamic range the ratio of the rms value of the signal to the rms su m of all other spectral components over the specified bandwidth. dynamic range is a signal-to-noise rati o measurement over the specified band width made with a -60 dbfs signal. 60 db is added to resulting measurement to refer the measurement to full-scale. this technique ensures that the distortion component s are below the noise level and do not effect the measurement. this measurement technique has be en accepted by the audio engineering society, aes17-1991, and the electronic industries associatio n of japan, eiaj cp-307. expressed in decibels. total harmonic distortion + noise the ratio of the rms value of the signal to the rms su m of all other spectral components over the specified band width (typically 10 hz to 20 khz), including dist ortion components. expressed in decibels. measured at -1 and -20 dbfs as suggested in aes17-1991 annex a. frequency response a measure of the amplitude response variation from 10 hz to 20 khz relative to the amplitude response at 1 khz. units in decibels. interchannel isolation a measure of crosstalk between the left and right cha nnels. measured for each c hannel at the converter's output with no signal to the input under test and a fu ll-scale signal applied to the other channel. units in decibels. interchannel gain mismatch the gain difference between left and right channels. units in decibels. gain error the deviation from the nominal full-scale a nalog output for a full-scale digital input. gain drift the change in gain value with te mperature. units in ppm/c. offset error the deviation of the mid-scale transition (111...111 to 000...000) from the ideal. units in mv.
ds603f1 61 CS42418 8. appendix a: external filters 8.1 adc input filter the analog modulator samples the i nput at 6.144 mhz (inter nal mclk=12.288 mhz). the digital filter will reject signals within the stopband of the filter. however, there is no rejection for input signals which are (n 6.144 mhz) the digital passband frequ ency, where n=0,1,2,... refer to figure 24 for a recommended analog input buffer that will attenuat e any noise energy at 6.144 mhz, in addition to providing the optimum source impedance for the modulators. the use of capa citors that have a large voltage coefficient (such as general-purpose ceramics) must be avoided since these can degrad e signal linearity. 8.2 dac output filter the CS42418 is a linear phase design and does not in clude phase or amplitude compensation for an exter- nal filter. therefore, the dac syste m phase and amplitude re sponse will be dependent on the external an- alog circuitry. va + + - - 100 f 100 k ? 10 k ? 3.32 k ? 2.8 k ? 0.1 f 100 f 470 pf 470 pf c0g c0g 634 ? 634 ? 634 ? 91 ? 91 ? 2700 pf c0g ainl1+ ainl1- ainr1+ ainr1- va + + - - 100 f 100 k ? 10 k ? 3.32 k ? 2.8 k ? 0.1 f 100 f 470 pf 470 pf c0g c0g 634 ? 634 ? 634 ? 91 ? 91 ? 2700 pf c0g 332 ? 332 ? figure 24. recommended analog input buffer ainl ainr aout + aout - - + 390 pf c0g 1 k ? 22 f 6.19 k ? 1800 pf c0g 887 ? 2.94 k ? 5.49 k ? 1.65 k ? 1.87 k ? 22 f 1200 pf c0g 5800 pf c0g 47.5 k ? analog out figure 25. recommended analog output buffer
62 ds603f1 CS42418 9. appendix b: pll filter 9.1 external filter components 9.1.1 general the pll behavior is affected by th e external filter component values in the typical connection diagrams. figure 5 and figure 6 show the recommended configuration of the two capacitors and one resistor that comprise the pll filter. the external pll component values listed in table 16 have a high corner-frequen- cy jitter-attenuation curve, take a sh ort time to lock, and offer good output jitter performance. lock times are worst case for an fs i transition of 192 khz. it is important to treat the lpfilt pin as a low-level analog input. it is suggested that the ground end of the pll filter be returned directly to the agnd pin independently of the digital ground plane. 9.1.2 capacitor selection the type of capacitors used for the pll filter can ha ve a significant effect on pll performance. large or exotic film capacitors are not necessary because thei r leads, and the required longer circuit board traces, add undesirable inductance to the ci rcuit. surface-mount ceramic capac itors are a good choice because their own inductance is low, and they can be mounted close to the lpflt pin to minimize trace induc- tance. for crip, a c0g or npo diel ectric is recommended; and for cfil t, an x7r dielectric is preferred. avoid capacitors with large temperature co-coefficient, or capacitors with high di electric constants, that are sensitive to shock and vibration. these include the z5u and y5v dielectrics. rfilt (k ? )cfilt ( f) crip (pf) 2.55 0.047 2200 table 16. pll external component values
ds603f1 63 CS42418 9.1.3 circuit board layout board layout and capacitor choice affect each other and determine the perfor mance of the pll. figure 26 illustrates a suggested layout fo r the pll filter compon ents and for bypassing th e analog supply volt- age. the 10 f bypass capacitor is an electrolytic in a surface-mount case a or thru-hole package. rfilt, cfilt, crip, and the 0.1 f decoupling capacitor are in an 0805 form factor. the 0.01 f decoupling capacitor is in the 0603 form factor. the traces are on the top surface of the board with the ic so that there is no via inductance. the traces themselves are short to minimize the inductance in the filter path. the va and agnd traces extend back to their origin an d are shown only in truncated form in the drawing. va agnd lpflt cfilt rfilt crip 0.1 f 0.01 f 10 f = via to ground plane figure 26. recommended layout example
64 ds603f1 CS42418 10.appendix c: adc filter plots -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 frequency (normalized to fs) amplitude (db) -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60 frequency (normalized to fs) amplitude (db) figure 27. single-speed mode stopband rejection figure 28. single-speed mode transition band -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0.45 0.46 0.47 0.48 0.49 0.50 0.51 0.52 0.53 0.54 0.55 frequency (normalized to fs) amplitude (db) -0.10 -0.08 -0.05 -0.03 0.00 0.03 0.05 0.08 0.10 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 frequency (normalized to fs) amplitude (db) figure 29. single-speed mode transition band (d etail) figure 30. single-speed mode passband ripple -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.00.10.20.30.40.50.60.70.80.91.0 frequency (normalized to fs) amplitude (db) -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.40 0.43 0.45 0.48 0.50 0.53 0.55 0.58 0.60 0.63 0.65 0.68 0.70 frequency (normalized to fs) amplitude (db) figure 31. double-speed mode stopband rejection figure 32. double-speed mode transition band
ds603f1 65 CS42418 ? -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0.40 0.43 0.45 0.48 0.50 0.53 0.55 frequency (normalized to fs) amplitude (db) -0.10 -0.08 -0.05 -0.03 0.00 0.03 0.05 0.08 0.10 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 frequency (normalized to fs) amplitude (db) figure 33. double-speed mode transition band (detail) figure 34. double-speed mode passband ripple -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.00.10.20.30.40.50.60.70.80.91.0 frequency (normalized to fs) amplitude (db) -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 frequency (normalized to fs) amplitude (db) figure 35. quad-speed mode stopband rejectio n figure 36. quad-speed mode transition band -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 frequency (normalized to fs) amplitude (db) -0.10 -0.08 -0.06 -0.04 -0.02 0.00 0.02 0.04 0.06 0.08 0.10 0.00 0.05 0.10 0.15 0.20 0.25 frequency (normalized to fs) amplitude (db) figure 37. quad-speed mode transition band (detail) figure 38. quad-speed mode passband ripple
66 ds603f1 CS42418 11.appendix d: dac filter plots 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0. 6 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 39. single-speed (fast) stopband rejectio n figure 40. single-speed (fast) transition band 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5 5 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0. 5 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) figure 41. single-speed (fast) transition band (detail) figure 42. single-speed (fast) passband ripple 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0. 6 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 43. single-speed (slow) stopband rejection figure 44. sing le-speed (slow) transition band
ds603f1 67 CS42418 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0. 5 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5 5 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) figure 45. single-speed (slow) transition band (d etail) figure 46. single-s peed (slow) passband ripple 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0. 6 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 47. double-speed (fast) stopband rejectio n figure 48. double-speed (fast) transition band 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5 5 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0. 5 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) figure 49. double-speed (fast) transition band (detail) figure 50. double-speed (fast) passband ripple
68 ds603f1 CS42418 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.2 0.3 0.4 0.5 0.6 0.7 0. 8 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 51. double-speed (slow) stopband rejection figure 52. doub le-speed (slow) transition band 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5 5 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.3 5 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) figure 53. double-speed (slow) transition band (d etail) figure 54. double-speed (slow) passband ripple 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.2 0.3 0.4 0.5 0.6 0.7 0. 8 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 55. quad-speed (fast) stopband rejection figure 56. quad-speed (fast) transition band
ds603f1 69 CS42418 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5 5 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.2 5 0.2 0.15 0.1 0.05 0 0.05 0.1 0.15 0.2 frequency(normalized to fs) amplitude (db) figure 57. quad-speed (fast) transition band (detail) figure 58. quad-speed (fast) passband ripple 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0. 9 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 59. quad-speed (slow) stopband rejectio n figure 60. quad-speed (slow) transition band 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5 5 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) 0 0.02 0.04 0.06 0.08 0.1 0.1 2 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) figure 61. quad-speed (slow) transition band (det ail) figure 62. quad-speed (slow) passband ripple
70 ds603f1 CS42418 12.package dimensions thermal characteristics inches millimeters dim min nom max min nom max a --- 0.55 0.063 --- 1.40 1.60 a1 0.002 0.004 0.006 0.05 0.10 0.15 b 0.007 0.008 0.011 0.17 0.20 0.27 d 0.461 0.472 bsc 0.484 11.70 12.0 bsc 12.30 d1 0.390 0.393 bsc 0.398 9.90 10.0 bsc 10.10 e 0.461 0.472 bsc 0.484 11.70 12.0 bsc 12.30 e1 0.390 0.393 bsc 0.398 9.90 10.0 bsc 10.10 e* 0.016 0.020 bsc 0.024 0.40 0.50 bsc 0.60 l 0.018 0.024 0.030 0.45 0.60 0.75 0.000 4 7.000 0.00 4 7.00 * nominal pin pitch is 0.50 mm controlling dimension is mm. jedec designation: ms026 parameter symbol min typ max units allowable junction temperature --+135 c junction to ambient thermal impedance ja -48 -c/watt 64l lqfp package drawing e1 e d1 d 1 e l b a1 a
ds603f1 71 CS42418 13.ordering information 14.references 1) cirrus logic, audio quality measurement specification , version 1.0, 1997. http://www.cirrus.com/products /papers/meas/meas.html 2) cirrus logic, an18: layout and design rules for data converters and other mixed signal devices , version 6.0, february 1998. 3) cirrus logic, techniques to meas ure and maximize the performance of a 120 db, 96 khz a/d con- verter integrated circuit , by steven harris, steven green and ka leung. presented at the 103rd con- vention of the audio engineer ing society, september 1997. 4) cirrus logic, a stereo 16-bit delta-sigma a/d converter for digital audio , by d.r. welland, b.p. del signore, e.j. swanson, t. tanaka, k. hamashita, s. hara, k. takasuka. paper presented at the 85th convention of the audio engineer ing society, november 1988. 5) cirrus logic, the effects of sampling clock jitter on nyquist sampling analog -to-digital converters, and on oversampling delta sigma adc's , by steven harris. paper presented at the 87th convention of the audio engineering society, october 1989. 6) cirrus logic, an 18-bit dual-channel oversampling delta-sigma a/d converter, with 19-bit mono ap- plication example , by clif sanchez. paper presented at th e 87th convention of the audio engineering society, october 1989. 7) cirrus logic, how to achieve optimum performance from delta-sigma a/d and d/a converters ,by steven harris. presented at the 93rd convention of the audio engineering society, october 1992. 8) cirrus logic, a fifth-order delta-sigma modulator with 110 db audio dynamic range , by i. fujimori, k. hamashita and e.j. swanson. paper presented at the 93rd convention of the audio engineering society, october 1992. 9) philips semiconductor, the i2c-bus specification: version 2.1 , january 2000. http://www.semicon- ductors.philips.com product description package pb-free grade temp range container order # CS42418 110 db, 192 khz 8-ch codec with pll 64-pin lqfp yes commercial -10 to +70 c tray CS42418-cqz tape & reel CS42418-cqzr automotive -40 to +85 c tray CS42418-dqz tape & reel CS42418-dqzr cdb42428 CS42418 evaluation board no - - - cdb42428
72 ds603f1 CS42418 15.revision history release date changes a1 may 2003 advance release a2 august 2004 added lead free part numbers. f1 november 2005 final release ? added revision history table on page 71 . ? updated registers 6.6.6 and 6.6.7 on page 47 . ? updated registers 6.7.4 and 6.7.5 on page 49 . ? updated pll components in table 16 on page 62 . ? added omck frequency specificatio n in the switchin g characteristics table on page 11 . ? updated adc input impedance and offset error specifications in the analog input characteristics table on page 7 . ? updated the dac full-scale voltage, output impedance, and gain drift specifications in the analog output characteristics table on page 9 . ? updated specification conditions for the analog input characteristics on page 7 . ? updated specification conditions for the analog output characteristics on page 9 . ? updated specification of t ds , t dh , t dpd , and t lrpd in the switching characteristics table on page 11 . ? corrected reference to the sw_ctrl[1:0] bits in section 4.4.3 on page 24 . ? moved the vq and filt+ specific ations from the analog input characteristics table on page 7 to the dc electrical characteristics table on page 14 . ? updated the power supply current and power consumption specifications in the dc electrical characteristics table on page 14 . ? updated section 4.4.4 on page 24 . ? corrected default value of the chip _id[3:0] bits in register 01h on pages 39 and 42 . ? updated default value of the rev_id[3:0] bits in register 01h on pages 39 and 42 . ? updated pll_clk[2:0] bit description on page 49 .
ds603f1 73 CS42418 contacting cirrus logic support for all product questions and inquiries co ntact a cirrus logic sales representative. to find the one nearest to you go to www.cirrus.com/corporate/contacts/sales.cfm important notice cirrus logic, inc. and its subsidiaries (?cirrus?) believe that the information contained in this document is accurate and reli able. however, the information is subject to change without notice and is provided ?as is? without warranty of any kind (express or implied). customers are advised to ob tain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold s ubject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liabil ity. no responsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for in fringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or impli ed under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights associated with the inf ormation contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. certain applications usin g semiconductor products may involve potential ri sks of death, personal injury, or severe prop- erty or environmental damage (?critical applications?). cirrus products are not designed, authorized or warranted for use in aircraft systems, military a pplications, products s urgically implanted into the body, automotive sa fety or security de- vices, life support products or other cri tical applications. i nclusion of cirrus products in su ch applications is understood to be fully at the customer?s risk and cirrus disclaims and makes no warranty, express, statutory or implied, including the implied warranties of merchantability and fitness for particular purp ose, with regard to any cirrus product that is used in such a manner. if the customer or cus tomer?s customer uses or permits the use of ci rrus products in critical applica- tions, customer agrees, by such use, to fully indemnify cirrus, its o fficers, directors, employee s, distributors and other agents from any and all liability, including attorneys? fees a nd costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners. spi is a trademark of motorola, inc.

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